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TTTech Computertechnik AG

Revision 2.1

11 - 20

AS8202NF TTP-C2NF

Note: All values not tested during production, guaranteed by design.

Figure 3. Read/Write Access Inactivity Time

14

RAM_CLK_TESTSE

Rising to READYB Rising

USE_RAM_CLK=1

3

9.7

ns

15

RAM_CLK_TESTSE

Rising to READYB

Deactivated 1->Z

USE_RAM_CLK

=1

Ready

delay='00'

3.6

12.9

ns

Ready

delay=01

4.5

15.4

Ready

delay=10

5.4

18.8

Ready

delay=11

6.4

22.2

16

Read to Read Access

Inactivity Time (CEB, OEB

low to CEB, OEB low)

min = 1.5 Tc

37.5

1

ns

17

Read to Write Access

Inactivity Time (CEB, OEB

low to CEB, WEB low)

5

1

ns

18

Write to Write Access

Inactivity Time (CEB, WEB

low to CEB, WEB low)

5

1,2

ns

19

Write to Read Access

Inactivity Time (CEB, WEB

low to CEB, OEB low)

5

1,2

ns

1. Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4,

8, 9). In addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19.

For more information on the inactivity times (see Figure 3).

2. To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal

CONTROLLER_ON register, CEB OEB and WEB have to be stable high within 200 ns (min = 8 Tc).

Table 6. Asynchronous DPRAM interface

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CEB

WEB

OEB

16

Read

Read

18

Write

17

Write

19

Read