www.austriamicrosystems.com and

TTTech Computertechnik AG

Revision 2.1

16 - 20

AS8202NF TTP-C2NF

TTP Synchronous Bus Interface

When in synchronous mode of operation, the bus unit uses a synchronous transfer method to transfer data at a rate

between 5 and 25 Mbit/s. The interface is designed to run at 25 Mbit/s and to be gluelessly compatible with the

commercial 100 Mbit/s Ethernet MII (Media Independent Interface) according to IEEE standard 802.3 (Ethernet CSMA/

CD).

Connecting the synchronous TTP bus unit to a 100 Mbit/s Ethernet PHY is done by connecting TxD, CTS, TxCLK,

RXER, RXCLK, RxDV and RxD of any channel to TxD0TxD0, TxEN, TxCLK, RXER, RXCLK, RxDV and RxD0 of the

COL and CRS as well as the MMII (Management Interface) should be left open or can be used for diagnostic purposes

by the application.

Note that the frames sent by the AS8202NF are not Ethernet compatible and that an Ethernet Hub (not a Switch) can

be used as a 'star coupler' for proper operation. Also note that the Ethernet PHY must be configured for Full Duplex

operation (even though the Hub does not support full duplex), because TTP has its own collision management that

should not interfere with the PHY's Half-Duplex collision management. In general, the PHY must not be configured for

automatic configuration ('Auto negotiation') but be hard-configured for 100 Mbit/s, Full Duplex operation.

Note: To run the interface at a rate other than 25 Mbit/s other transceiver PHY components have to be used.

Test Interface

The Test Interface supports the manufacturing test and characterization of the chip. In the application environment test

pins have to be connected as following:

of the application.

Table 13. Synchronous Bus Interface Connections

Pin Name

Mode

Connect to PHY

Note

TxD[0]

out

TxD0TxD0

Transmit data channel 0

CTS[0]

out

TxEN

Transmit enable channel 0

TxCLK[0]

in

TxCLK

Transmit clock channel 0

RXER[0]

in

RXER

Receive error channel 0

RXCLK[0]

in

RXCLK

Receive clock channel 0

RxDV[0]

in

RxDV

Receive data valid channel 0

RxD[0]

in

RxD0

Receive data channel 0

TxD[1]

out

TxD0

Transmit data channel 1

CTS[1]

out

TxEN

Transmit enable channel 1

TxCLK[1]

in

TxCLK

Transmit clock channel 1

RXER[1]

in

RXER

Receive error channel 1

RXCLK[1]

in

RXCLK

Receive clock channel 1

RxDV[1]

in

RxDV

Receive data valid channel 1

RxD[1]

in

RxD0

Receive data channel 1