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TTTech Computertechnik AG

Revision 2.1

13 - 20

AS8202NF TTP-C2NF

Reset and Oscillator

External Reset Signal

To issue a reset of the chip the RESETB port has to be driven low for at least 1 us. Pulses under 50 ns duration are

discarded. At power-up the reset must overlap the build-up time of the power supply.

Integrated Power-On Reset

The Device has an internal Power-On Reset generator. When supply voltage ramps up, the internal reset signal is kept

active (low) for 33 µs typical.

Note: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid

and oscillator inputs active.

Oscillator Circuitry

The internal oscillators for main and bus guardian clock require external quartzes or external oscillators. The main

clock features a PLL multiplying a 10 MHz XIN0/XOUT0 oscillation to an internal frequency of 40 MHz when enabled.

Figure 9. Main clock setup

Rf will normally not be soldered, it is only provided to get maximum flexibility.

Cext, typ = 15/18 pF. Rd has to be calculated, if the measured drive level will be too high; if drive level is ok, Rd = 0.

Table 7. Pin mode

Pin Name

Mode

Comment

XIN0

analog

main oscillator input (external clock input)

XOUT0

analog

main oscillator output

XIN1

analog

bus guardian oscillator input (external clock input)

XOUT1

analog

bus guardian oscillator output

PLLOFF

in

PLL disable

RESETB

in

external reset

Table 8. Parameters

Symbol

Parameter

Min

Typ

Max

Unit

dV/dt

supply voltage slope

551

-

-

V/ms

tpores

25

33

49

µs

VS S

10 M Hz

Rd

Rf

Cext

Cext

VSS

10 MHz

square

wave

VDD

40 MHz

square

wave

Enabled PLL, external quartz

Enabled PLL, external oscillator

Disabled PLL, external oscillator