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WM8816 Datasheet(PDF) 4 Page - Wolfson Microelectronics plc |
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WM8816 Datasheet(HTML) 4 Page - Wolfson Microelectronics plc |
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4 / 12 page  WM8816 Advanced Information WOLFSON MICROELECTRONICS LTD AI Rev 1.1 September 2000 4 TEST CONDITIONS AVDD = 5.0V, AGND = 0V, TA = 25°C, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Performance Gain = 0dB 13 N Gain = -60dB 4 µV rms Noise (Note 1) VIN = 0V, VOUT with OP275, A-weighed Gain = mute 2.5 Total Harmonic Distortion plus Noise THD+N VIN= 1Vrms, gain=0dB, VOUT with OP275, DC to 20 kHz 0.001 (100) % (dB) Dynamic Range (Note 1) DR 120 130 dB Crosstalk (Note 1) CR Between channels, gain=0dB, fIN=1kHz -100 -110 dB Digital Inputs / Outputs Input low voltage VIL All digital inputs 0.3 DVDD V Input high voltage VIH All digital inputs 0.7 DVDD V Output low voltage VOL ILoad = 2mA 0.4 V Output high voltage VOH ILoad = 2mA DVDD -0.4 V Control Interface Timing Clock Frequency fCCLK 1MHz Period of CCLK high tWHC VIH to VIH 500 ns Period of CCLK low tWLC VIL to VIL 500 ns Rise time of CCLK tRC VIL to VIH 100 ns Fall time of CCLK tFC VIH to VIL 100 ns Hold time, CCLK high to CSB low tHCHS 20 ns Setup time, CSB low to CCLK high tSSLCH 100 ns Setup time, valid DATA to CCLK high tSDCH 100 ns Hold time, CCLK high to invalid DATA tHCHD 100 ns Setup time, CCLK low to valid DATA tDCLD Load = 100pF 200 ns Hold time, CSB high or 16 th CCLK low to invalid DATA tDSZ Load = 3.3k Ω 20 200 ns Hold time, 16 th CCLK high to CSB high tHLCHS 200 ns Setup time, CSB high to CCLK high tSSHCH 200 ns Note: 1. Guaranteed by design. |
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