AM1707 datasheet(101/198 Pages) TI

101 / 198 page

AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-48. McASP0 Switching Characteristics(1)

No.

PARAMETER

MIN

MAX

UNIT

Cycle time, AHCLKR0 internal, AHCLKR0 output

Cycle time, AHCLKR0 external, AHCLKR0 output

tc(AHCLKRX)

Cycle time, AHCLKX0 internal, AHCLKX0 output

Cycle time, AHCLKX0 external, AHCLKX0 output

Pulse duration, AHCLKR0 internal, AHCLKR0 output

(AHR/2) – 2.5(2)

Pulse duration, AHCLKR0 external, AHCLKR0 output

(AHR/2) – 2.5(2)

tw(AHCLKRX)

Pulse duration, AHCLKX0 internal, AHCLKX0 output

(AHX/2) – 2.5(3)

Pulse duration, AHCLKX0 external, AHCLKX0 output

(AHX/2) – 2.5(3)

Cycle time, ACLKR0 internal, ACLKR0 output

greater of 2P or 20 ns(4)

Cycle time, ACLKR0 external, ACLKR0 output

greater of 2P or 20 ns(4)

tc(ACLKRX)

Cycle time, ACLKX0 internal, ACLKX0 output

greater of 2P or 20 ns(4)

Cycle time, ACLKX0 external, ACLKX0 output

greater of 2P or 20 ns(4)

Pulse duration, ACLKR0 internal, ACLKR0 output

(AR/2) – 2.5(5)

Pulse duration, ACLKR0 external, ACLKR0 output

(AR/2) – 2.5(5)

tw(ACLKRX)

Pulse duration, ACLKX0 internal, ACLKX0 output

(AX/2) – 2.5(6)

Pulse duration, ACLKX0 external, ACLKX0 output

(AX/2) – 2.5(6)

Delay time, ACLKR0 internal, AFSR output(7)

Delay time, ACLKX0 internal, AFSX output

Delay time, ACLKR0 external input, AFSR output(7)

11.7

td(ACLKRX-AFSRX)

Delay time, ACLKX0 external input, AFSX output

11.7

Delay time, ACLKR0 external output, AFSR output(7)

11.7

Delay time, ACLKX0 external output, AFSX output

11.7

Delay time, ACLKX0 internal, AXR0[n] output

td(ACLKX-AXRV)

Delay time, ACLKX0 external input, AXR0[n] output

2.75

11.7

Delay time, ACLKX0 external output, AXR0[n] output

11.7

Disable time, ACLKX0 internal, AXR0[n] output

tdis(ACLKX-AXRHZ)

Disable time, ACLKX0 external input, AXR0[n] output

11.7

Disable time, ACLKX0 external output, AXR0[n] output

11.7

(1)

McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

AHR - Cycle time, AHCLKR0.

(3)

AHX - Cycle time, AHCLKX0.

(4)

P = SYSCLK2 period

(5)

AR - ACLKR0 period.

(6)

AX - ACLKX0 period.

(7)

McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

Peripheral Information and Electrical Specifications

101

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