AM1707 datasheet(104/198 Pages) TI

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AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

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6.17.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing

Table 6-51 and Table 6-52 assume testing over recommended operating conditions (see Figure 6-34 and

Figure 6-35).

Table 6-51. McASP2 Timing Requirements(1) (2)

No.

PARAMETER

MIN

MAX

UNIT

Cycle time, AHCLKR2 external, AHCLKR2 input

tc(AHCLKRX)

Cycle time, AHCLKX2 external, AHCLKX2 input

Pulse duration, AHCLKR2 external, AHCLKR2 input

6.5

tw(AHCLKRX)

Pulse duration, AHCLKX2 external, AHCLKX2 input

6.5

Cycle time, ACLKR2 external, ACLKR2 input

greater of 2P or 13

tc(ACLKRX)

Cycle time, ACLKX2 external, ACLKX2 input

greater of 2P or 13

Pulse duration, ACLKR2 external, ACLKR2 input

6.5

tw(ACLKRX)

Pulse duration, ACLKX2 external, ACLKX2 input

6.5

Setup time, AFSR2 input to ACLKR2 internal(3)

Setup time, AFSX2 input to ACLKX2 internal

Setup time, AFSR2 input to ACLKR2 external input(3)

1.6

tsu(AFSRX-ACLKRX)

Setup time, AFSX2 input to ACLKX2 external input

1.6

Setup time, AFSR2 input to ACLKR2 external output(3)

1.6

Setup time, AFSX2 input to ACLKX2 external output

1.6

Hold time, AFSR2 input after ACLKR2 internal(3)

-1.9

Hold time, AFSX2 input after ACLKX2 internal

-2

Hold time, AFSR2 input after ACLKR2 external input(3)

1.4

th(ACLKRX-AFSRX)

Hold time, AFSX2 input after ACLKX2 external input

1.4

Hold time, AFSR2 input after ACLKR2 external output(3)

1.4

Hold time, AFSX2 input after ACLKX2 external output

1.4

Setup time, AXR2[n] input to ACLKR2 internal(3)

Setup time, AXR2[n] input to ACLKX2 internal(4)

Setup time, AXR2[n] input to ACLKR2 external input(3)

1.6

tsu(AXR-ACLKRX)

Setup time, AXR2[n] input to ACLKX2 external input(4)

1.6

Setup time, AXR2[n] input to ACLKR2 external output(3)

1.6

Setup time, AXR2[n] input to ACLKX2 external output(4)

1.6

Hold time, AXR2[n] input after ACLKR2 internal(3)

-2.2

Hold time, AXR2[n] input after ACLKX2 internal(4)

-2.2

Hold time, AXR2[n] input after ACLKR2 external input(3)

1.3

th(ACLKRX-AXR)

Hold time, AXR2[n] input after ACLKX2 external input(4)

1.3

Hold time, AXR2[n] input after ACLKR2 external output(3)

1.3

Hold time, AXR2[n] input after ACLKX2 external output(4)

1.3

(1)

ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

P = SYSCLK2 period

(3)

McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2

(4)

McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2

104

Peripheral Information and Electrical Specifications

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