AM1707 datasheet(105/198 Pages) TI

105 / 198 page

AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-52. McASP2 Switching Characteristics(1)

No.

PARAMETER

MIN

MAX

UNIT

Cycle time, AHCLKR2 internal, AHCLKR2 output

Cycle time, AHCLKR2 external, AHCLKR2 output

tc(AHCLKRX)

Cycle time, AHCLKX2 internal, AHCLKX2 output

Cycle time, AHCLKX2 external, AHCLKX2 output

Pulse duration, AHCLKR2 internal, AHCLKR2 output

(AHR/2) – 2.5(2)

Pulse duration, AHCLKR2 external, AHCLKR2 output

(AHR/2) – 2.5(2)

tw(AHCLKRX)

Pulse duration, AHCLKX2 internal, AHCLKX2 output

(AHX/2) – 2.5(3)

Pulse duration, AHCLKX2 external, AHCLKX2 output

(AHX/2) – 2.5(3)

Cycle time, ACLKR2 internal, ACLKR2 output

greater of 2P or 13 ns(4)

Cycle time, ACLKR2 external, ACLKR2 output

greater of 2P or 13 ns(4)

tc(ACLKRX)

Cycle time, ACLKX2 internal, ACLKX2 output

greater of 2P or 13 ns(4)

Cycle time, ACLKX2 external, ACLKX2 output

greater of 2P or 13 ns(4)

Pulse duration, ACLKR2 internal, ACLKR2 output

(AR/2) – 2.5(5)

Pulse duration, ACLKR2 external, ACLKR2 output

(AR/2) – 2.5(5)

tw(ACLKRX)

Pulse duration, ACLKX2 internal, ACLKX2 output

(AX/2) – 2.5(6)

Pulse duration, ACLKX2 external, ACLKX2 output

(AX/2) – 2.5(6)

Delay time, ACLKR2 internal, AFSR output(7)

-1.4

2.8

Delay time, ACLKX2 internal, AFSX output

-1.4

2.8

Delay time, ACLKR2 external input, AFSR output(7)

2.6

td(ACLKRX-AFSRX)

Delay time, ACLKX2 external input, AFSX output

2.9

Delay time, ACLKR2 external output, AFSR output(7)

2.9

Delay time, ACLKX2 external output, AFSX output

2.9

Delay time, ACLKX2 internal, AXR2[n] output

-1.4

2.8

td(ACLKX-AXRV)

Delay time, ACLKX2 external input, AXR2[n] output

2.75

Delay time, ACLKX2 external output, AXR2[n] output

2.75

Disable time, ACLKX2 internal, AXR2[n] output

-1.4

2.8

tdis(ACLKX-AXRHZ)

Disable time, ACLKX2 external input, AXR2[n] output

2.9

Disable time, ACLKX2 external output, AXR2[n] output

2.9

(1)

McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1

McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

AHR - Cycle time, AHCLKR2.

(3)

AHX - Cycle time, AHCLKX2.

(4)

P = SYSCLK2 period

(5)

AR - ACLKR2 period.

(6)

AX - ACLKX2 period.

(7)

McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2

Peripheral Information and Electrical Specifications

105

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