AM1707 datasheet(111/198 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

6.18.2 SPI Electrical Data/Timing

6.18.2.1 Serial Peripheral Interface (SPI) Timing

Table 6-54 through Table 6-69 assume testing over recommended operating conditions (see Figure 6-38

through Figure 6-41).

Table 6-54. General Timing Requirements for SPI0 Master Modes(1)

No.

PARAMETER

MIN

MAX

UNIT

greater of 2P or

tc(SPC)M

Cycle Time, SPI0_CLK, All Master Modes

256P

20 ns

tw(SPCH)M

Pulse Width High, SPI0_CLK, All Master Modes

0.5tc(SPC)M - 1

tw(SPCL)M

Pulse Width Low, SPI0_CLK, All Master Modes

0.5tc(SPC)M - 1

Polarity = 0, Phase = 0,

to SPI0_CLK rising

Polarity = 0, Phase = 1,

- 0.5tc(SPC)M + 5

to SPI0_CLK rising

Delay, initial data bit valid on SPI0_SIMO

td(SIMO_SPC)M

after initial edge on SPI0_CLK(2)

Polarity = 1, Phase = 0,

to SPI0_CLK falling

Polarity = 1, Phase = 1,

- 0.5tc(SPC)M + 5

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid on

from SPI0_CLK falling

td(SPC_SIMO)M

SPI0_SIMO after transmit edge of

Polarity = 1, Phase = 0,

SPI0_CLK

from SPI0_CLK falling

Polarity = 1, Phase = 1,

from SPI0_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M -3

from SPI0_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)M -3

from SPI0_CLK rising

Output hold time, SPI0_SIMO valid

toh(SPC_SIMO)M

afterreceive edge of SPI0_CLK

Polarity = 1, Phase = 0,

0.5tc(SPC)M -3

from SPI0_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)M -3

from SPI0_CLK falling

Polarity = 0, Phase = 0,

to SPI0_CLK falling

Polarity = 0, Phase = 1,

to SPI0_CLK rising

Input Setup Time, SPI0_SOMI valid

tsu(SOMI_SPC)M

beforereceive edge of SPI0_CLK

Polarity = 1, Phase = 0,

to SPI0_CLK rising

Polarity = 1, Phase = 1,

to SPI0_CLK falling

Polarity = 0, Phase = 0,

from SPI0_CLK falling

Polarity = 0, Phase = 1,

from SPI0_CLK rising

Input Hold Time, SPI0_SOMI valid after

tih(SPC_SOMI)M

receive edge of SPI0_CLK

Polarity = 1, Phase = 0,

from SPI0_CLK rising

Polarity = 1, Phase = 1,

from SPI0_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

Peripheral Information and Electrical Specifications

111

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