AM1707 datasheet(115/198 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-59. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

1.5 P -3

2.5 P + 18.5

from SPI0_CLK falling

Delay from final

Polarity = 0, Phase = 1,

– 0.5tc(SPC)M + 1.5 P -3

– 0.5tc(SPC)M + 2.5 P + 18.5

SPI0_CLK edge

from SPI0_CLK falling

td(SPC_ENAH)S

to slave

Polarity = 1, Phase = 0,

deasserting

1.5 P -3

2.5 P + 18.5

from SPI0_CLK rising

SPI0_ENA.

Polarity = 1, Phase = 1,

– 0.5tc(SPC)M + 1.5 P -3

– 0.5tc(SPC)M + 2.5 P + 18.5

from SPI0_CLK rising

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-55 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 6-60. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Required delay from SPI0_SCS asserted at slave to first

td(SCSL_SPC)S

SPI0_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P+5

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P+5

Required delay from final

from SPI0_CLK falling

td(SPC_SCSH)S

SPI0_CLK edge before SPI0_SCS

Polarity = 1, Phase = 0,

is deasserted.

0.5tc(SPC)M + P+5

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P+5

from SPI0_CLK rising

Delay from master asserting SPI0_SCS to slave driving

tena(SCSL_SOMI)S

P + 18.5

SPI0_SOMI valid

Delay from master deasserting SPI0_SCS to slave 3-stating

tdis(SCSH_SOMI)S

P + 18.5

SPI0_SOMI

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-55 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Peripheral Information and Electrical Specifications

115

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