AM1707 datasheet(117/198 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-62. General Timing Requirements for SPI1 Master Modes (1) (continued)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

0.5tc(SPC)M -3

from SPI1_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)M -3

Output hold time, SPI1_SIMO from SPI1_CLK rising

toh(SPC_SIMO)M

valid after

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

0.5tc(SPC)M -3

from SPI1_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)M -3

from SPI1_CLK falling

Polarity = 0, Phase = 0,

to SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Setup Time,

to SPI1_CLK rising

tsu(SOMI_SPC)M

SPI1_SOMI valid before

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

to SPI1_CLK rising

Polarity = 1, Phase = 1,

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI1_SOMI

from SPI1_CLK rising

tih(SPC_SOMI)M

valid after receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

from SPI1_CLK rising

Polarity = 1, Phase = 1,

from SPI1_CLK falling

Table 6-63. General Timing Requirements for SPI1 Slave Modes(1)

No.

PARAMETER

MIN

MAX

UNIT

tc(SPC)S

Cycle Time, SPI1_CLK, All Slave Modes

greater of 2P or 20 ns

256P

tw(SPCH)S

Pulse Width High, SPI1_CLK, All Slave Modes

tw(SPCL)S

Pulse Width Low, SPI1_CLK, All Slave Modes

Polarity = 0, Phase = 0,

to SPI1_CLK rising

Polarity = 0, Phase = 1,

Setup time, transmit data

to SPI1_CLK rising

written to SPI before initial

tsu(SOMI_SPC)S

clock edge from

Polarity = 1, Phase = 0,

master.(2) (3)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid

from SPI1_CLK falling

td(SPC_SOMI)S

on SPI1_SOMI after transmit

Polarity = 1, Phase = 0,

edge of SPI1_CLK

from SPI1_CLK falling

Polarity = 1, Phase = 1,

from SPI1_CLK rising

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.

(3)

Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus

cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Peripheral Information and Electrical Specifications

117

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