AM1707 datasheet(120/198 Pages) TI

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AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-66. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3) (continued)

No.

PARAMETER

MIN

MAX

UNIT

Max delay for slave SPI to drive SPI1_ENA

td(SCSL_ENAL)M

valid after master asserts SPI1_SCS to delay

C2TDELAY + P

the master from beginning the next transfer.

Polarity = 0, Phase = 0,

2P -5

to SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay from

0.5tc(SPC)M + 2P -5

to SPI1_CLK rising

SPI1_SCS active to

td(SCS_SPC)M

first SPI1_CLK(7) (8)

Polarity = 1, Phase = 0,

2P -5

(9)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 2P -5

to SPI1_CLK falling

Polarity = 0, Phase = 0,

3P + 3

to SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay from assertion

0.5tc(SPC)M + 3P + 3

to SPI1_CLK rising

of SPI1_ENA low to

td(ENA_SPC)M

first SPI1_CLK

Polarity = 1, Phase = 0,

3P + 3

edge.(10)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 3P + 3

to SPI1_CLK falling

(7)

If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.

(8)

In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(9)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.

Table 6-67. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

1.5 P -3

2.5 P + 19

from SPI1_CLK falling

Delay from

Polarity = 0, Phase = 1,

final

– 0.5tc(SPC)M + 1.5 P -3

– 0.5tc(SPC)M + 2.5 P + 19

from SPI1_CLK falling

SPI1_CLK

td(SPC_ENAH)S

edge to slave

Polarity = 1, Phase = 0,

1.5 P -3

2.5 P + 19

deasserting

from SPI1_CLK rising

SPI1_ENA.

Polarity = 1, Phase = 1,

– 0.5tc(SPC)M + 1.5 P -3

– 0.5tc(SPC)M + 2.5 P + 19

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-63 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

Table 6-68. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Required delay from SPI1_SCS asserted at slave to first

td(SCSL_SPC)S

SPI1_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 5

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P + 5

Required delay from final

from SPI1_CLK falling

td(SPC_SCSH)S

SPI1_CLK edge before

Polarity = 1, Phase = 0,

SPI1_SCS is deasserted.

0.5tc(SPC)M + P + 5

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P + 5

from SPI1_CLK rising

Delay from master asserting SPI1_SCS to slave driving

tena(SCSL_SOMI)S

P + 19

SPI1_SOMI valid

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-63 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

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