AM1707 datasheet(121/198 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-68. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2) (3) (continued)

No.

PARAMETER

MIN

MAX

UNIT

Delay from master deasserting SPI1_SCS to slave

tdis(SCSH_SOMI)S

P + 19

3-stating SPI1_SOMI

Table 6-69. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Required delay from SPI1_SCS asserted at slave to

td(SCSL_SPC)S

first SPI1_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 5

from SPI1_CLK falling

Polarity = 0, Phase = 1,

P + 5

Required delay from final

from SPI1_CLK falling

td(SPC_SCSH)S

SPI1_CLK edge before

Polarity = 1, Phase = 0,

SPI1_SCS is deasserted.

0.5tc(SPC)M + P + 5

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P + 5

from SPI1_CLK rising

Delay from master asserting SPI1_SCS to slave

tena(SCSL_SOMI)S

P + 19

driving SPI1_SOMI valid

Delay from master deasserting SPI1_SCS to slave

tdis(SCSH_SOMI)S

P + 19

3-stating SPI1_SOMI

Delay from master deasserting SPI1_SCS to slave

tena(SCSL_ENA)S

driving SPI1_ENA valid

Polarity = 0, Phase = 0,

2.5 P + 19

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Delay from final clock

2.5 P + 19

from SPI1_CLK rising

receive edge on SPI1_CLK

tdis(SPC_ENA)S

to slave 3-stating or driving

Polarity = 1, Phase = 0,

2.5 P + 19

high SPI1_ENA.(4)

from SPI1_CLK rising

Polarity = 1, Phase = 1,

2.5 P + 19

from SPI1_CLK falling

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-63 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(4)

SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is

3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying

several SPI slave devices to a single master.

Peripheral Information and Electrical Specifications

121

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