AM1707 datasheet(118/198 Pages) TI

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AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

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Table 6-63. General Timing Requirements for SPI1 Slave Modes (1) (continued)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

0.5tc(SPC)S -3

from SPI1_CLK falling

Polarity = 0, Phase = 1,

0.5tc(SPC)S -3

Output hold time, SPI1_SOMI from SPI1_CLK rising

toh(SPC_SOMI)S

valid after receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

0.5tc(SPC)S -3

from SPI1_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)S -3

from SPI1_CLK falling

Polarity = 0, Phase = 0,

to SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Setup Time,

to SPI1_CLK rising

tsu(SIMO_SPC)S

SPI1_SIMO valid before

Polarity = 1, Phase = 0,

receive edge of SPI1_CLK

to SPI1_CLK rising

Polarity = 1, Phase = 1,

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI1_SIMO

from SPI1_CLK rising

tih(SPC_SIMO)S

valid after receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

from SPI1_CLK rising

Polarity = 1, Phase = 1,

from SPI1_CLK falling

Table 6-64. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

3P + 3

to SPI1_CLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 3P + 3

to SPI1_CLK rising

Delay from slave assertion of SPI1_ENA

td(EN A_SPC)M

active to first SPI1_CLK from master.(4)

Polarity = 1, Phase = 0,

3P + 3

to SPI1_CLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 3P + 3

to SPI1_CLK falling

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 5

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Max delay for slave to deassert

P + 5

from SPI1_CLK falling

SPI1_ENA after final SPI1_CLK edge to

td(SPC_ENA)M

ensure master does not begin the next

Polarity = 1, Phase = 0,

0.5tc(SPC)M + P + 5

transfer.(5)

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P + 5

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-62 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI1_ENA assertion.

(5)

In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

118

Peripheral Information and Electrical Specifications

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