AM1707 datasheet(116/198 Pages) TI

116 / 198 page

AM1707

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

www.ti.com

Table 6-61. Additional(1) SPI0 Slave Timings, 5-Pin Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Required delay from SPI0_SCS asserted at slave to first

td(SCSL_SPC)S

SPI0_CLK edge at slave.

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P + 5

from SPI0_CLK falling

Polarity = 0, Phase = 1,

P + 5

Required delay from final

from SPI0_CLK falling

td(SPC_SCSH)S

SPI0_CLK edge before

Polarity = 1, Phase = 0,

SPI0_SCS is deasserted.

0.5tc(SPC)M + P + 5

from SPI0_CLK rising

Polarity = 1, Phase = 1,

P + 5

from SPI0_CLK rising

Delay from master asserting SPI0_SCS to slave driving

tena(SCSL_SOMI)S

P + 18.5

SPI0_SOMI valid

Delay from master deasserting SPI0_SCS to slave

tdis(SCSH_SOMI)S

P + 18.5

3-stating SPI0_SOMI

Delay from master deasserting SPI0_SCS to slave driving

tena(SCSL_ENA)S

18.5

SPI0_ENA valid

Polarity = 0, Phase = 0,

2.5 P + 18.5

from SPI0_CLK falling

Polarity = 0, Phase = 1,

Delay from final clock receive

2.5 P + 18.5

from SPI0_CLK rising

edge on SPI0_CLK to slave

tdis(SPC_ENA)S

3-stating or driving high

Polarity = 1, Phase = 0,

2.5 P + 18.5

SPI0_ENA.(4)

from SPI0_CLK rising

Polarity = 1, Phase = 1,

2.5 P + 18.5

from SPI0_CLK falling

(1)

These parameters are in addition to the general timings for SPI slave modes ( Table 6-55 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(4)

SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is

3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying

several SPI slave devices to a single master.

Table 6-62. General Timing Requirements for SPI1 Master Modes(1)

No.

PARAMETER

MIN

MAX

UNIT

tc(SPC)M

Cycle Time, SPI1_CLK, All Master Modes

greater of 2P or 20 ns

256P

tw(SPCH)M

Pulse Width High, SPI1_CLK, All Master Modes

0.5tc(SPC)M - 1

tw(SPCL)M

Pulse Width Low, SPI1_CLK, All Master Modes

0.5tc(SPC)M - 1

Polarity = 0, Phase = 0,

to SPI1_CLK rising

Polarity = 0, Phase = 1,

- 0.5tc(SPC)M + 5

Delay, initial data bit valid on

to SPI1_CLK rising

td(SIMO_SPC)M

SPI1_SIMO to initial edge on

Polarity = 1, Phase = 0,

SPI1_CLK(2)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

- 0.5tc(SPC)M + 5

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid

from SPI1_CLK falling

td(SPC_SIMO)M

on SPI1_SIMO after transmit

Polarity = 1, Phase = 0,

edge of SPI1_CLK

from SPI1_CLK falling

Polarity = 1, Phase = 1,

from SPI1_CLK rising

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.

116

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): AM1707

AM1707 Datasheet(PDF) 116 Page - Texas Instruments

AM1707 Datasheet(HTML) 116 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL