AM1707 datasheet(119/198 Pages) TI

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AM1707

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SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

Table 6-65. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase =

2P -5

to SPI1_CLK rising

Polarity = 0, Phase =

0.5tc(SPC)M + 2P -5

to SPI1_CLK rising

Delay from SPI1_SCS active to first

td(SCS_SPC)M

SPI1_CLK(4) (5)

Polarity = 1, Phase =

2P -5

to SPI1_CLK falling

Polarity = 1, Phase =

0.5tc(SPC)M + 2P -5

to SPI1_CLK falling

Polarity = 0, Phase =

0.5tc(SPC)M + P - 3

from SPI1_CLK

falling

Polarity = 0, Phase =

P - 3

from SPI1_CLK

Delay from final SPI1_CLK edge to master

td(SPC_SCS)M

falling

deasserting SPI1_SCS (6) (7)

Polarity = 1, Phase =

0.5tc(SPC)M + P -3

from SPI1_CLK rising

Polarity = 1, Phase =

P - 3

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-62 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(5)

This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain

asserted.

(7)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Table 6-66. Additional(1) SPI1 Master Timings, 5-Pin Option(2) (3)

No.

PARAMETER

MIN

MAX

UNIT

Polarity = 0, Phase = 0,

0.5tc(SPC)M+P+5

from SPI1_CLK falling

Max delay for slave to

deassert SPI1_ENA

Polarity = 0, Phase = 1,

P+5

after final SPI1_CLK

from SPI1_CLK falling

td(SPC_ENA)M

edge to ensure

Polarity = 1, Phase = 0,

master does not

0.5tc(SPC)M+P+5

from SPI1_CLK rising

begin the next

transfer.(4)

Polarity = 1, Phase = 1,

P+5

from SPI1_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M + P -3

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Delay from final

P - 3

from SPI1_CLK falling

SPI1_CLK edge to

td(SPC_SCS)M

master deasserting

Polarity = 1, Phase = 0,

0.5tc(SPC)M+ P -3

SPI1_SCS (5) (6)

from SPI1_CLK rising

Polarity = 1, Phase = 1,

P - 3

from SPI1_CLK rising

(1)

These parameters are in addition to the general timings for SPI master modes ( Table 6-63 ).

(2)

P = SYSCLK2 period

(3)

Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)

In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

(5)

Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain

asserted.

(6)

This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Peripheral Information and Electrical Specifications

119

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