| Electronic Components Datasheet Search |
|
AM1808AZCED3 Datasheet(PDF) 40 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM1808AZCED3 Datasheet(HTML) 40 Page - Texas Instruments |
|
40 / 264 page ![]() AM1808 SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 3.7.16 Multichannel Buffered Serial Ports (McBSP) Table 3-18. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions SIGNAL POWER TYPE(1) PULL(2) DESCRIPTION GROUP(3) NAME NO. McBSP0 AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] F3 I CP[6] A McBSP0 sample rate generator clock input / CLKS0 AXR6 / CLKR0 / GP1[14] / MII_TXEN / C1 I/O CP[5] A McBSP0 receive clock PRU0_R31[6] AXR4 / FSR0 / GP1[12] / MII_COL D1 I/O CP[5] A McBSP0 receive frame sync AXR2 / DR0 / GP1[10] / MII_TXD[2] E2 I CP[5] A McBSP0 receive data AXR5 / CLKX0 / GP1[13] / MII_TXCLK D3 I/O CP[5] A McBSP0 transmit clock AXR3 / FSX0 / GP1[11] / MII_TXD[3] E3 I/O CP[5] A McBSP0 transmit frame sync AXR1 / DX0 / GP1[9] / MII_TXD[1] E1 O CP[5] A McBSP0 transmit data McBSP1 AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / E4 I CP[3] A McBSP1 sample rate generator clock input PRU0_R31[8] AXR14 / CLKR1 / GP0[6] B4 I/O CP[2] A McBSP1 receive clock AXR12 / FSR1 / GP0[4] C4 I/O CP[2] A McBSP1 receive frame sync AXR10 / DR1 / GP0[2] D4 I CP[2] A McBSP1 receive data AXR13 / CLKX1 / GP0[5] B3 I/O CP[2] A McBSP1 transmit clock AXR11 / FSX1 / GP0[3] C5 I/O CP[2] A McBSP1 transmit frame sync AXR9 / DX1 / GP0[1] C3 O CP[2] A McBSP1 transmit data (1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. 40 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |