AM1808AZCED3 datasheet(102/264 Pages) TI

102 / 264 page

AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

www.ti.com

Table 6-21. Timing Requirements for EMIFA Asynchronous Memory Interface (1)

1.3V, 1.2V

1.1V

1.0V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

READS and WRITES

tc(CLK)

Cycle time, EMIFA module clock

tw(EM_WAIT)

Pulse duration, EM_WAIT assertion and deassertion

READS

tsu(EMDV-EMOEH)

Setup time, EM_D[15:0] valid before EM_OE high

th(EMOEH-EMDIV)

Hold time, EM_D[15:0] valid after EM_OE high

Setup Time, EM_WAIT asserted before end of Strobe

tsu (EMOEL-EMWAIT)

4E+3

Phase(2)

WRITES

Setup Time, EM_WAIT asserted before end of Strobe

tsu (EMWEL-EMWAIT)

4E+3

Phase(2)

(1)

E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when

SYSCLK3 is selected and set to 100MHz, E=10ns

(2)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended

wait states. Figure 6-14 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)

1.3V, 1.2V, 1.1V, 1.0V

PARAMETER

UNIT

MIN

Nom

MAX

READS and WRITES

td(TURNAROUND)

Turn around time

(TA)*E - 3

(TA)*E

(TA)*E + 3

READS

(RS+RST+RH)*E

EMIF read cycle time (EW = 0)

(RS+RST+RH)*E

- 3

+ 3

tc(EMRCYCLE)

(RS+RST+RH+(E

(RS+RST+RH+(EW (RS+RST+RH+(E

EMIF read cycle time (EW = 1)

WC*16))*E - 3

C*16))*E

WC*16))*E + 3

Output setup time, EMA_CE[5:2] low to

(RS)*E-3

(RS)*E

(RS)*E+3

EMA_OE low (SS = 0)

tsu(EMCEL-EMOEL)

Output setup time, EMA_CE[5:2] low to

-3

EMA_OE low (SS = 1)

Output hold time, EMA_OE high to

(RH)*E - 3

(RH)*E

(RH)*E + 3

EMA_CE[5:2] high (SS = 0)

th(EMOEH-EMCEH)

Output hold time, EMA_OE high to

-3

EMA_CE[5:2] high (SS = 1)

Output setup time, EMA_BA[1:0] valid to

tsu(EMBAV-EMOEL)

(RS)*E-3

(RS)*E

(RS)*E+3

EMA_OE low

Output hold time, EMA_OE high to

th(EMOEH-EMBAIV)

(RH)*E-3

(RH)*E

(RH)*E+3

EMA_BA[1:0] invalid

Output setup time, EMA_A[13:0] valid to

tsu(EMBAV-EMOEL)

(RS)*E-3

(RS)*E

(RS)*E+3

EMA_OE low

Output hold time, EMA_OE high to

th(EMOEH-EMAIV)

(RH)*E-3

(RH)*E

(RH)*E+3

EMA_A[13:0] invalid

(1)

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle

Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],

WH[8-1], and MEW[1-256].

(2)

E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when

SYSCLK3 is selected and set to 100MHz, E=10ns.

(3)

EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that

the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.

102

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): AM1808

AM1808AZCED3 Datasheet(PDF) 102 Page - Texas Instruments

AM1808AZCED3 Datasheet(HTML) 102 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL