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AM1808AZCED3 Datasheet(PDF) 192 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 192 Page - Texas Instruments |
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192 / 264 page  MII_RXCLK 2 3 1 MII_TXCLK 2 3 1 MII_RXCLK(Input) 1 2 MII_RXD[3]-MII_RXD[0], MII_RXDV,MII_RXER(Inputs) AM1808 SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com 6.22.1.1 EMAC Electrical Data/Timing Table 6-98. Timing Requirements for MII_RXCLK (see Figure 6-45) 1.3V, 1.2V, 1.1V 1.0V NO. 10 Mbps 100 Mbps 10 Mbps UNIT MIN MAX MIN MAX MIN MAX 1 tc(MII_RXCLK) Cycle time, MII_RXCLK 400 40 400 ns 2 tw(MII_RXCLKH) Pulse duration, MII_RXCLK high 140 14 140 ns 3 tw(MII_RXCLKL) Pulse duration, MII_RXCLK low 140 14 140 ns Figure 6-45. MII_RXCLK Timing (EMAC - Receive) Table 6-99. Timing Requirements for MII_TXCLK (see Figure 6-45) 1.3V, 1.2V, 1.1V 1.0V NO. PARAMETER 10 Mbps 100 Mbps 10 Mbps UNIT MIN MAX MIN MAX MIN MAX 1 tc(MII_TXCLK) Cycle time, MII_TXCLK 400 40 400 ns 2 tw(MII_TXCLKH) Pulse duration, MII_TXCLK high 140 14 140 ns 3 tw(MII_TXCLKL) Pulse duration, MII_TXCLK low 140 14 140 ns Figure 6-46. MII_TXCLK Timing (EMAC - Transmit) Table 6-100. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-47) 1.3V, 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX 1 tsu(MRXD-MII_RXCLKH) Setup time, receive selected signals valid before MII_RXCLK high 8 ns 2 th(MII_RXCLKH-MRXD) Hold time, receive selected signals valid after MII_RXCLK high 8 ns (1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER. Figure 6-47. EMAC Receive Interface Timing 192 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
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