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TLC5916IPWR Datasheet(PDF) 7 Page - Texas Instruments |
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TLC5916IPWR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 30 page  www.ti.com Recommended Operating Conditions Recommended Timing TLC5916, TLC5917 8-BIT CONSTANT-CURRENT LED SINK DRIVERS SLVS695A – JUNE 2007 – REVISED MARCH 2008 CONDITIONS MIN MAX UNIT VDD Supply voltage 3 5.5 V VO Supply voltage to output pins OUT0–OUT7 17 V VO ≥ 0.6 V 5 IO Output current DC test circuit mA VO ≥ 1 V 120 IOH High-level output current source SDO shorted to GND –1 mA IOL Low-level output current sink SDO shorted to VCC 1 mA VIH High-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0.7 × V DD VDD V VIL Low-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0 0.3 × V DD V VDD = 3 V to 5.5 V (unless otherwise noted) CONDITIONS MIN MAX UNIT tw(L) LE(ED1) pulse duration Normal Mode 20 ns tw(CLK) CLK pulse duration Normal Mode 20 ns Normal Mode, IOUT < 60 mA 500 tw(OE) OE(ED2) pulse duration ns Normal Mode, IOUT > 60 mA 700 tsu(D) Setup time for SDI Normal Mode 3 ns th(D) Hold time for SDI Normal Mode 2 ns tsu(L) Setup time for LE(ED1) Normal Mode 15 ns th(L) Hold time for LE(ED1) Normal Mode 15 ns tw(CLK) CLK pulse duration Error Detection Mode 20 ns tw(ED2) OE(ED2) pulse duration Error Detection Mode 2000 ns tsu(ED1) Setup time for LE(ED1) Error Detection Mode 4 ns th(ED1) Hold time for LE(ED1) Error Detection Mode 10 ns tsu(ED2) Setup time for OE(ED2) Error Detection Mode 6 ns th(ED2) Hold time for OE(ED2) Error Detection Mode 10 ns fCLK Clock frequency Cascade operation 30 MHz Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TLC5916 TLC5917 |
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