CDCE62005 datasheet(70/80 Pages) TI

70 / 80 page

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30.72 MHz

10.00 MHz

122 .88 MHz

491 .52 MHz

245 .76 MHz

30.72 MHz

10 MHz

20 log

jitter

total

SNR

πf jitter

(

)

(

)

total

ADC

CLK

jitter

6.02

1.76

ADC

SNR

CDCE62005

SCAS862C – NOVEMBER 2008 – REVISED FEBRUARY 2010

www.ti.com

Figure 44. CDCE62005 Jitter Cleaner Example

Clocking ADCs with the CDCE62005

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample

clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly

implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation

trend often causes engineers working in communications system design to encounter the term clock limited

performance. Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation 10

shows the relationship of data converter signal to noise ratio (SNR) to total jitter.

(10)

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample

clock:

(11)

With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation

shows the relationship between resolution and SNR:

(12)

Figure 45 plots Equation 10 and Equation 12 for constant values of total jitter. When used in conjunction with

most ADCs, the CDCE62005 supports a total jitter performance value of <1 ps.

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