TAS5631 datasheet(9/33 Pages) TI

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TAS5631

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SLES221C – JULY 2009 – REVISED APRIL 2010

AUDIO SPECIFICATION (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%)

and a TAS5631 power stage. PCB and system configurations are in accordance with recommended guidelines. Audio

frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 2 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C;

output filter: LDEM = 7 mH, CDEM = 1 mF, MODE = 101-00, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RL = 2 Ω, 10%, THD+N, clipped input signal

600

RL = 3 Ω, 10%, THD+N, clipped input signal

400

RL = 4 Ω, 10%, THD+N, unclipped input signal

300

Power output per channel

RL = 2 Ω, 1% THD+N, unclipped input signal

480

RL = 3 Ω, 1% THD+N, unclipped input signal

310

RL = 4 Ω, 1% THD+N, unclipped input signal

230

THD+N

Total harmonic distortion + noise

1 W

0.03%

Output integrated noise

A-weighted, TAS5518 modulator

170

SNR

Signal-to-noise ratio(1)

A-weighted, TAS5518 modulator

103

A-weighted, input level –60 dBFS using

DNR

Dynamic range

103

TAS5518 modulator

Pidle

Power dissipation due to idle losses (IPVDD_X)

PO = 0, 4 channels switching

(2)

3.7

(1)

SNR is calculated relative to 1% THD-N output level.

(2)

Actual system idle losses are affected by core losses of output inductors.

ELECTRICAL CHARACTERISTICS

PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as reference

VREG

VDD = 12 V

3.3

3.6

node, VREG

VI_CM

Analog comparator reference node, VI_CM

1.5

1.75

1.9

Operating, 50% duty cycle

22.5

IVDD

VDD supply current

Idle, reset mode

22.5

50% duty cycle

12.5

IGVDD_x

Gate-supply current per half-bridge

Reset mode

1.5

50% duty cycle without output filter or

19.5

load

IPVDD_x

Half-bridge idle current

Reset mode, no switching

750

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

TJ = 25°C, excludes metallization

100

Ω

resistance,

RDS(on)

Drain-to-source resistance, high side (HS)

100

Ω

GVDD = 12 V

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