P89LPC985 datasheet(52/85 Pages) NXP

52 / 85 page

P89LPC980_982_983_985_2

Preliminary data sheet

Rev. 02 — 8 February 2010

52 of 85

NXP Semiconductors

P89LPC980/982/983/985

8-bit microcontroller with accelerated two-clock 80C51 core

7.25 Analog comparators

Two analog comparators are provided on the P89LPC980/982/983/985. Input and output

options allow use of the comparators in a number of different configurations. Comparator

operation is such that the output is a logical one (which may be read in a register and/or

routed to a pin) when the positive input (one of two selectable pins) is greater than the

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be configured to cause an interrupt when the

output value changes.

The overall connections to both comparators are shown in Figure 18. The comparators

function to VDD =2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are not

guaranteed to be stable for 10

μs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt flag must be cleared before the

interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COn, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will

cause an interrupt if the comparator interrupt is enabled. The user should therefore

disable the comparator interrupt prior to disabling the comparator. Additionally, the user

should clear the comparator flag, CMFn, after disabling the comparator.

Fig 17. SPI single master multiple slaves configuration

002aaa903

master

slave

8-BIT SHIFT

SPI CLOCK

GENERATOR

8-BIT SHIFT

MISO

MOSI

SPICLK

port

MISO

MOSI

SPICLK

slave

8-BIT SHIFT

MISO

MOSI

SPICLK

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