PCA9505 datasheet(2/31 Pages) NXP

2 / 31 page

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

2 of 31

NXP Semiconductors

PCA9505/06

40-bit I2C-bus I/O port with RESET, OE and INT

I Inputs:

N Programmable Interrupt Mask Control for input pins that do not require an interrupt

when their states change

N Polarity Inversion register allows inversion of the polarity of the I/O pins when read

I Active LOW reset (RESET) input pin resets device to power-up default state

I 3 programmable address pins allowing 8 devices on the same bus

I Designed for live insertion

N Minimize line disturbance (IOFF and power-up 3-state)

N Signal transient rejection (50 ns noise ﬁlter and robust I2C-bus state machine)

I Low standby current

I −40 °Cto+85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA

I Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages

Applications

I Servers

I RAID systems

I Industrial control

I Medical equipment

I PLCs

I Cell phones

I Gaming machines

I Instrumentation and test measurement

Ordering information

Table 1.

Ordering information

Type number

Topside mark

Package

Name

Description

Version

PCA9505DGG

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

PCA9506DGG

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

PCA9506BS

HVQFN56

plastic thermal enhanced very thin quad ﬂat package;

no leads; 56 terminals; body 8

× 8 × 0.85 mm

SOT684-1

PCA9505 Datasheet(PDF) 2 Page - NXP Semiconductors

PCA9505 Datasheet(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL