PCF8566 datasheet(17/48 Pages) NXP

17 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

17 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

When display data is transmitted to the PCF8566 the display bytes received are stored in

the display RAM based on the selected LCD drive mode. An example of a 7-segment

numeric display illustrating the storage order for all drive modes is shown in Figure 11.

The RAM storage organization applies equally to other LCD types.

The following applies to Figure 11:

• Static drive mode: the eight transmitted data bits are placed in row 0 to eight

successive display RAM addresses.

• 1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to

four successive display RAM addresses.

• 1:3 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1 and 2 of

three successive addresses, with bit 2 of the third address left unchanged. This last bit

can, if necessary, be controlled by an additional transfer to this address but avoid

overriding adjacent data because always full bytes are transmitted.

• 1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and

3 to two successive display RAM addresses.

7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load data pointer command (see Table 13). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 11).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD conﬁguration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

Fig 10. Display RAM bit map showing the direct relationship between display RAM

addresses and segment outputs and between bits in a RAM word and backplane

outputs

1234

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

mgg389

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