PCF8566 datasheet(20/48 Pages) NXP

20 / 48 page

PCF8566_7

Product data sheet

Rev. 07 — 25 February 2009

20 of 48

NXP Semiconductors

PCF8566

Universal LCD driver for low multiplex rates

An additional feature is for an arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. Using the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

speciﬁed by the blink select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at ﬁxed time

intervals.

If the entire display needs to be blinked at a frequency other than the nominal blinking

frequency, this can be done using the mode set command to set and reset the display

enable bit E at the required rate (see Table 9).

Basic architecture

8.1 Characteristics of the I2C-bus

The I2C-bus provides bidirectional, two-line communication between different IC or

modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When

connected to the output stages of a device, both lines must be connected to a positive

supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 12.

Table 7.

Blink frequencies

Blinking mode

Normal operating

mode ratio

Power saving mode

ratio

Blink frequency

off

blinking off

2 Hz

1 Hz

0.5 Hz

blink

clk

92160

----------------

blink

elk

15360

----------------

blink

clk

184320

--------------------

blink

clk

30720

----------------

blink

clk

368640

--------------------

blink

clk

61440

----------------

Fig 12. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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