TDA9984A datasheet(28/40 Pages) NXP

28 / 40 page

TDA9984A_4

Product data sheet

Rev. 04 — 15 January 2009

28 of 40

NXP Semiconductors

TDA9984A

HDMI 1.3 transmitter with 1080p upscaler embedded

8.7 I2C-bus interface

The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant. Pin I2C_SCL is only an input

pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The

registers of the TDA9984A can be accessed via the I2C-bus. All registers are R/W except

some, which cannot be read for conﬁdentiality.

The TDA9984A is used as a slave I2C-bus device. Bits A0 and A1 of the I2C-bus device

address are externally selected by pins A0 and A1 (see Table 18).

The I2C-bus access format is shown in Figure 16.

Firstly, the master writes the TDA9984A address and the subaddress to access the

speciﬁc register, and then the data.

I2C-bus registers deﬁnitions

9.1 Memory page management

The I2C-bus memory is split into several pages and the selection between pages is made

with common register CURPAGE_ADR. It is only necessary to write in this register once

to change the current page. So multiple read or write operations in the same page need a

write register CURPAGE_ADR once at the beginning.

9.2 ID version

The ID-version readable via I2C-bus is deﬁned as follows:

Table 18.

Device address

W/R

11100

pin A1

pin A0

0/1

Fig 16. I2C-bus access

001aaf292

123456789123456789123456789

SLAVE ADDRESS

SUBADDRESS

SCL

SDA

DATA

STOP

Table 19.

Memory pages

Page address

Memory page description

00h

general control

01h

scaler and PLL scaling

02h

PLL settings

09h

EDID control page

10h

InfoFrames and packets

11h

audio settings and content info packets

12h

HDCP and OTP

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