HT68F03 datasheet(81/139 Pages) HOLTEK

81 / 139 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.00

April 16, 2010

¨ TM2BL Register

Bit

76543210

Name

R/W

POR

00000000

Bit7~0

TM2BL: TM2 CCRB Low Byte Register bit 7~bit 0

TM2 10-bit CCRB bit 7~bit 0

¨ TM2BH Register

Bit

76543210

Name

¾¾¾¾¾¾

R/W

¾¾¾¾¾¾

R/W

POR

¾¾¾¾¾¾

Bit 7~2

Unimplemented, read as

²0²

Bit 1~0

TM2BH: TM2 CCRB High Byte Register bit 1~bit 0

TM2 10-bit CCRB bit 9 ~ bit 8

Enhanced Type TM Operating Modes

The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output

Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using

the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register.

ETM Operating Mode

CCRA

Compare Match

Output Mode

CCRA

Timer/Counter

Mode

CCRA PWM

Output Mode

CCRA Single

Pulse Output

Mode

CCRA Input

Capture Mode

CCRB Compare Match Output Mode

ÖÖÖ

CCRB Timer/Counter Mode

ÖÖÖ

CCRB PWM Output Mode

ÖÖÖ

CCRB Single Pulse Output Mode

¾Ö¾

CCRB Input Capture Mode

Ö¾Ö

Note:

²Ö² allowed to be used. ²¾²: not allowed to be used

Compare Output Mode

To select this mode, bits TnAM1, TnAM0 and TnBM1,

TnBM0 in the TMnC1/TMnC2 registers should be all

cleared to zero. In this mode once the counter is en-

abled and running it can be cleared by three methods.

These are a counter overflow, a compare match from

Comparator A and a compare match from Comparator

P. When the TnCCLR bit is low, there are two ways in

which the counter can be cleared. One is when a com-

pare match occurs from Comparator P, the other is when

the CCRP bits are all zero which allows the counter to

overflow. Here both the TnAF and TnPF interrupt re-

quest flags for Comparator A and Comparator P respec-

tively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the

counter will be cleared when a compare match occurs

from Comparator A. However, here only the TnAF inter-

rupt request flag will be generated even if the value of

the CCRP bits is less than that of the CCRA registers.

Therefore when TnCCLR is high no TnPF interrupt re-

quest flag will be generated.

HT68F03 Datasheet(PDF) 81 Page - Holtek Semiconductor Inc

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