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LTC3829 Datasheet(PDF) 14 Page - Linear Technology |
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LTC3829 Datasheet(HTML) 14 Page - Linear Technology |
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14 / 40 page ![]() LTC3829 3829f operaTion (Refer to Functional Diagram) A phase-locked loop (PLL) is available on the LTC3829 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN pin. The PLL loop filter network is integrated inside the LTC3829. The phase- locked loop is capable of locking any frequency within the range of 250kHz to 770kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. The controller is operating in forced continuous mode when it is synchronized. Sensing the Output Voltage with a Differential Amplifier The LTC3829 includes a low offset, unity-gain, high band- widthdifferentialamplifierforapplicationsthatrequiretrue remote sensing. Sensing the load across the load capaci- torsdirectlygreatlybenefitsregulationinhighcurrent,low voltage applications, where board interconnection losses can be a significant portion of the total error budget. TheLTC3829differentialamplifierhasatypicaloutputslew rate of 2V/µs. The amplifier is configured for unity gain, meaning that the difference between DIFFP and DIFFN is translated to DIFFOUT, relative to SGND. Care should be taken to route the DIFFP and DIFFN PCB traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, the DIFFP and DIFFN traces should be shielded by a low impedance ground plane to maintain signal integrity. The maximum output voltage when using the differential amplifierisINTVCC–1.4V(typically3.6V).Abovethisoutput voltage the differential amplifier should not be used. Power Good (PGOOD Pin) The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 0.6V reference voltage. The PGOOD pin is also pulled low when the RUN pin is below 1.22V or when the LTC3829 is in the soft-start or tracking phase. When the VFB pin voltage is within the ±10% regulation window, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when the VFBpiniswithintheregulationwindow.However, there is an internal 100µs power-bad mask when the VFB goes out of the window. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. In such cases, the topMOSFETisturnedoffandthebottomMOSFETisturned on until the overvoltage condition is cleared. Undervoltage Lockout The LTC3829 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCCvoltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.3V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 600mV of precision hysteresis. Anotherwaytodetectanundervoltageconditionistomoni- tor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. The RUN comparator itself has about 80mV of hysteresis. One can program additional hysteresis for the RUN comparator by adjusting the val- ues of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4.5V. |
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