ADS1258IPHPREP datasheet(36/57 Pages) TI

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DRDY

NEW Bit

Data Reads

(register format)

ADS1258-EP

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

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CHANNEL DATA

The data read operation outputs either four bytes (one byte for status and three bytes for data), or three bytes for

data only. The selection of 4-byte or 3-byte data read is set by the bit STAT in register CONFIG0 (see Table 13,

Status Byte, for options). In the 4-byte read, the first byte is the status byte and the following three bytes are the

data bytes. The MSB (Data23) of the data is shifted out first.

Table 10. CHANNEL DATA FORMAT

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

STATUS

NEW

OVF

SUPPLY

CHID4

CHID3

CHID2

CHID1

CHID0

MSB

Data23

Data22

Data21

Data20

Data19

Data18

Data17

Data16

MSB-1

Data15

Data14

Data13

Data12

Data11

Data10

Data9

Data8

LSB

Data7

Data6

Data5

Data4

Data3

Data2

Data1

Data0

STATUS BYTE

BIT STATUS.7, NEW

The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit

remains set indefinitely until the channel data is read. When the channel data is read again before the converter

updates with new data, the previous data is output and the NEW bit is cleared. If the channel data is not read

before the next conversion update, the data from the previous conversion is lost. As shown in Figure 62, the

NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY output pin in

software, the user reads data at a rate faster than the converter's data rate. The user then polls the NEW bit to

detect for new channel data.

0 = Channel data has not been updated since the last read operation.

1 = Channel data has been updated since the last read operation.

Figure 62. NEW Bit Operation

BIT STATUS.6 OVF

When this bit is set, this indicates the differential voltage applied to the ADC inputs have exceeded the range of

the converter |VIN| > 1.06 VREF. During over-range, the output code of the converter clips to either positive FS

(VIN ≥ 1.06 × VREF) or negative FS (VIN ≤

–1.06 × VREF). This bit, with the MSB of the data, can be used to

detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital

filter, the absence of this bit does not assure that the modulator of the ADC has not saturated due to possible

transient input overload conditions.

BIT STATUS.5 SUPPLY

This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit

is set when the value falls below 4.3 V (typically) and is reset when the value rises 50mV higher (typically) than

the lower trip point. The output data of the ADC may not be valid under low power-supply conditions.

BITS CHID[4:0] CHANNEL ID BITS

The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode,

the Channel ID bits are undefined. See Table 11 for the channel ID, the measurement priority, and the channel

description for Auto-Scan Mode.

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