ADS1258IPHPREP datasheet(26/57 Pages) TI

26 / 57 page

ADC

Multiplexer

(chopping)

AINn

MUXOUTP

MUXOUTN

ADCINP

Optional

Signal

Conditioning

ADCINN

GPIO Pin

GPIO Data (read)

GPIO Data (write)

GPIO Control

ADS1258-EP

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

www.ti.com

EXTERNAL CHOPPING

GPIO DIGITAL PORT (GPIOx)

The modulator of the ADS1258 incorporates a

The

ADS1258

has

eight

dedicated

pins

for

chopping front-end which removes offset errors,

General-Purpose Digital I/O (GPIO). The digital I/O

providing excellent offset and offset drift performance.

pins are individually configurable as either inputs or

However, offset and offset drift originating from

as outputs through the GPIOC (GPIO-Configure)

external signal conditioning are not removed by the

modulator. The ADS1258 has an additional chopping

the level of the pins. When reading the GPIOD

feature that removes external offset errors (CHOP =

1).

whether they are programmed as inputs or outputs.

As inputs, a write to the GPIOD has no effect. As

With external chopping enabled, the converter takes

outputs, a write to the GPIOD sets the output value.

two readings in succession on the same channel. The

first reading is taken with one polarity and the second

During Standby and Power-Down modes, the GPIO

reading is taken with the opposite polarity. The

remains active. If configured as inputs, they must be

converter averages the two readings, canceling the

driven (do not float). If configured as outputs, they

offset, as shown in Figure 49. With chopping enabled,

continue to drive the pins. The GPIO pins are set as

the effective reading is reduced to half of the nominal

inputs after power-on or after a reset. Figure 50

reading rate.

shows the GPIO port structure.

Figure 49. External Chopping

Figure 50. GPIO Port Pin

Note that since the inputs are reversed under control

of the ADS1258, a delay time may be necessary to

provide time for external signal conditioning to fully

POWER-DOWN INPUT (PWDN)

settle before the second phase of the reading

The PWDN pin is used to control the power-down

sequence starts (see the Switch time Delay section).

mode of the converter. In power-down mode, all

External chopping can be used to significantly reduce

internal circuitry is deactivated including the oscillator

total offset errors (to less than 10

μV) and offset drift

and the clock output. Hold PWDN low for at least two

over temperature (to less than 0.2

μV/°C). Note that

fCLK cycles to engage power-down. The register

chopping must be disabled (CHOP = 0) to take the

settings are retained during power-down. When the

internal monitor readings.

pin is returned high, the converter requires a wake-up

time before readings can be taken, as shown in the

Power-Up Timing section. Note that in power-down

mode, the inputs of the ADS1258 must still be driven

and the device continues to drive the outputs.

Submit Documentation Feedback

Product Folder Link(s): ADS1258-EP

ADS1258IPHPREP Datasheet(PDF) 26 Page - Texas Instruments

ADS1258IPHPREP Datasheet(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL