ADS1258IPHPREP datasheet(38/57 Pages) TI

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ADS1258-EP

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

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COMMAND AND REGISTER DEFINITIONS

Commands are used to read channel data, access the configuration registers, and control the conversion

process. If the command is a register read or write operation, one or more data bytes follow the command byte.

If bit MUL = 1 in the command byte, then multiple registers can be read or written in one command operation

(see the MUL bit). Commands can be sent back-to-back without toggling CS; however, after a channel Data

Read Direct operation, CS must be toggled or an SPI timeout must occur before sending a command. The data

read by command does not require CS to be toggled.

The command byte consists of three fields: the Command Bits(C[2:0]), multiple register access bit (MUL), and

the Register Address Bits (A[3:0]); see the Command Byte register.

Command Byte

MUL

Bits C[2:0] — Command Bits

These bits code the command within the command byte.

C[2:0]

DESCRIPTION

COMMENTS

000

Channel Data Read Direct (no command)

Toggle CS or allow SPI timeout before sending command

001

Channel Data Read Command (register format)

Set MUL = 1; status byte always included in data

010

011

100

Pulse Convert Command

MUL, A[3:0] are don't care

101

Reserved

110

Reset Command

MUL, A[3:0] don't care

111

Channel Data Read Direct (no command)

Toggle CS or allow SPI timeout before sending command

Bit 4 MUL: Multiple Register Access

0 = Disable Multiple Register Access

1 = Enable Multiple Register Access

This bit enables the multiple register access. This option allows writing or reading more than one register in a

single command operation. If only one register is to be read or written, set MUL = '0'. For multiple register

access, set MUL = '1'. The read or write operation begins at the addressed register. The ADS1258 automatically

increments the register address for each register data byte subsequently read or written. The multiple register

read or write operations complete after register address = 09h (device ID register) has been accessed.

The multiple register access is terminated in one of three ways:

1. The user takes CS high. This action resets the SPI interface.

2. The user holds SCLK inactive for 4096 fCLK cycles. This action resets the SPI interface.

3. Register address = 09h has been accessed. This completes the command and the ADS1258 is then ready

for a new command. Note for the Channel Data Read command, this bit must be set to read the four data

bytes (one status byte and three data bytes).

A[3:0] Register Address Bits

These bits are the register addresses for a register read or write operation; see Table 12.

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