TL16CP754C datasheet(39/49 Pages) TI

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WR THR

DTRx

1 Baud Time

Controlled by DLY[3:0]

TL16CP754C, TL16CM754C, TL16C754C

www.ti.com

SLLS644E – DECEMBER 2007 – REVISED MAY 2010

Table 24. LOOP and RCVEN Functionality

LOOP MODE

RCVEN

AFR

MODE

DESCRIPTION

Receive threshold, timeout, and error detection interrupts available.

AFR = 10

RS-232

Data stored in receive FIFO.

Receive threshold, timeout, and error detection interrupts available.

RCVEN = 1

AFR = 14

RS-485

Data stored in receive FIFO.

LOOP mode off,

Receive threshold, timeout, and error detection interrupts available.

AFR = 12

IrDA

MCR4 = 0,

Data stored in receive FIFO.

RX, TX active

Receive threshold and error detection interrupts available.

AFR = 00

RS-232

Data stored in receive FIFO.

RCVEN = 0

AFR = 04

RS-485

No data stored in receive FIFO, hence no interrupts available.

AFR = 02

IrDA

No data stored in receive FIFO, hence no interrupts available.

Receive threshold, timeout, and error detection interrupts available.

AFR = 10

RS-232

Data stored in receive FIFO.

Receive threshold, timeout, and error detection interrupts available.

RCVEN = 1

AFR = 14

RS-485

Data stored in receive FIFO.

Receive threshold, timeout, and error detection interrupts available.

AFR = 12

IrDA

LOOP mode on,

Data stored in receive FIFO.

MCR4 = 1,

Receive threshold and error detection interrupts available.

RX, TX inactive

AFR = 00

RS-232

Data stored in receive FIFO.

Receive threshold and error detection interrupts available.

RCVEN = 0

AFR = 04

RS-485

Data stored in receive FIFO.

Receive threshold and error detection interrupts available.

AFR = 02

IrDA

Data stored in receive FIFO.

RS-485 Mode

The RS-485 mode is intended to simplify the interface between the UART channel and an RS-485 driver or

transceiver. When enabled by setting 485EN, the DTRx output goes high one bit time before the first start bit of

the first data byte being sent, and remains high as long as there is pending data in the transmitter shift register

(TSR) or transmitter holding register (THR, xmt fifo). Once both are empty (after the last stop bit of the last data

byte), the DTRx output stays high for a programmable delay of 0 to 15 bit times, as set by DLY[3:0]. This helps

preserve data integrity over long signal lines. This is illustrated in the following.

Often RS-485 packets are relatively short and the entire packet can fit within the 64 byte xmt fifo. In this case, it

goes empty when the TSR goes empty. But in cases where a larger block needs to be sent, it is advantageous to

reload the xmt fifo as soon as it is depleted. Otherwise, the transmission stalls while waiting for the xmt fifo to be

reloaded, which varies with processor load. In this case, it is best to also set 485LG (large block) which causes

the transmit interrupt to occur wither when the THR becomes empty (if the xmt fifo level was not above the

threshold), or when the xmt fifo threshold is crossed. The reloading of the xmt fifo occurs while some data is

being shifted out, eliminating fifo underrun. If desired, when the last bytes of a current transmission are being

loaded in the xmt fifo, 485LG can be cleared before the load and the transmit interrupt occurs on the TSR going

empty.

Waveforms are not shown to scale, as the WR THR pulses typically are less than 100 ns, where the TX waveform

varies with baud rate but is typically in the microsecond range.

Figure 24. DTRx and Transmit Data Relationship

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