56F8013 datasheet(73/126 Pages) FREESCALE

73 / 126 page

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

•

01001 = Reserved for factory test—OCCS MSTR OSC clock

•

01011 = Reserved for factory test—ADC clock

•

01100 = Reserved for factory test—JTAG TCLK

•

01101 = Reserved for factory test—Continuous peripheral clock

•

01110 = Reserved for factory test—Continuous inverted peripheral clock

•

01111 = Reserved for factory test—Continuous high-speed peripheral clock

6.3.8

SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. To

select peripheral or GPIO control, program corresponding bit in the GPIOx_PEREN register in GPIO

module. See the 56F801x Peripheral Reference Manual for detail. In some cases, there are two possible

peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS

peripheral mode.

As shown in Figure 6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which

pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when

PEREN = 1.

Figure 6-9 Overall Control of Pads Using SIM_GPS Control

Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)

Base + $B

Read

TCR

PCR

CFG_

CFG_A5

CFG_A4

Write

RESET

0000000

0000

GPIOB_PEREN Register

GPIO Controlled

I/O Pad Control

SIM_GPS Register

Quad Timer Controlled

SCI Controlled

56F8013 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc

56F8013 Datasheet(HTML) 73 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL