56F8013 datasheet(79/126 Pages) FREESCALE

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Clock Generation Overview

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO)

6.3.10.3

Input/Output Short Address Location (ISAL[21:6])—Bits 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.4 Clock Generation Overview

The SIM uses master clocks, 2X system clock at a maximum of 64MHz, from the OCCS module to

produce the peripheral and system (core and memory) clocks at a maximum of 32MHz. It divides the

master clock by two and gates it with appropriate power mode and clock gating controls. The high speed

peripheral clock from OCCS operates at three times the system clock for PWM and Quad Timer module

at a maximum of 96MHz.

The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either

an external clock or the relaxation oscillator can be selected as the master clock source (MSTR_OSC). The

relaxation oscillator can be operated at full speed (8MHz), standby speed (200kHz), or powered down. An

8MHz clock can be multiplied to 192 MHz using the PLL and postscaled to provide a variety of high speed

clock rates. Either the postscaled PLL output or input clock of PLL signal can be selected to produce the

master clocks to the SIM. When the PLL is not selected, the high speed peripheral clock is disabled and

the 2X system clock is input clock from either internal relaxation oscillator or external clock source.

In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables

(SIM_PCE register, CLK_DIS, ONCE_EBL), and clock rate controls (TCR, PCR) to provide flexible

control of clocking and power utilization. The SIM’s clock enable controls can be used to disable

individual clocks when not needed. The clock rate controls enable the high speed clocking option for the

Timer channels and PWM but require the PLL to be on and selected. Refer to the 56F801X Peripheral

User Manual for further details.

6.5 Power-Down Modes

The 56F8013/56F8011 operates in one of five Power-Down modes, as shown in Table 6-3

Base + $E

Read

ISAL[21:6]

Write

RESET

11111

Table 6-3 Clock Operation in Power-Down Modes

Mode

Core Clocks

Peripheral Clocks

Description

Run

Core and memory

clocks disabled

Peripheral clocks

enabled

Device is fully functional

56F8013 Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc

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