56F8013 datasheet(74/126 Pages) FREESCALE

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56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

6.3.8.1

Quad Timer Clock Rate (TCR)—Bit 15

This bit selects the clock speed for the Quad Timermodule.

•

0 = Quad Timer module clock rate equals system clock rate, to a maximum 32MHz (default)

•

1 = Quad Timer module clock rate equals three times system clock rate, to a maximum 96MHz

Note: This bit should only be changed while the TMR module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM sync signal pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section

6.3.1.7), then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

6.3.8.2

PWM Clock Rate (PCR)—Bit 14

This bit selects the clock speed for the PWM module.

•

0 = PWM module clock rate equals system clock rate, to a maximum 32MHz (default)

•

1 = PWM module clock rate equals three times system clock rate, to a maximum 96MHz

Note: This bit should only be changed while the PWM module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM sync signal is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7),

then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

6.3.8.3

Reserved—Bits 13–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.8.4

Configure GPIOB7 (CFG_B7)—Bit 11

This bit selects the alternate function for GPIOB7.

•

0 = TXD — SCI Transmit Data (default)

•

1 = SCL — I2C Serial Clock

6.3.8.5

Configure GPIOB6 (CFG_B6)—Bit 10

This bit selects the alternate function for GPIOB6.

Table 6-2 Allowable Quad Timer and PWM Clock Rates

when Using PWM Reload Pulse

Quad Timer

Clock Speed

PWM

56F8013 Datasheet(PDF) 74 Page - Freescale Semiconductor, Inc

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