FS6377

3.0 Functional Block Description

3.1 Phase Locked Loops (PLLs)

Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a

desired frequency by a ratio of integers. This frequency multiplication is exact.

As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop

filter, a voltage-controlled oscillator (VCO), and a feedback divider.

continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at

the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:

Figure 3: PLL Diagram

3.1.1. Reference Divider

The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-

down frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by

programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.

3.1.2. Feedback Divider

The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully

programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also

called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO

can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall

power consumption of the divider.

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