OPA830IDBVT datasheet(20/35 Pages) TI

20 / 35 page

OPA830

SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

www.ti.com

OPA830

+5V

−5V

Ω

750

Ω

348

Ω

ΩSource

150

Ω

750

Ω

6.8

µF

6.8

µF

0.1

µF

0.1

µF

0.01

µF

Figure 3. DC-Coupled, G = +2, Bipolar Supply

Specification and Test Circuit

SINGLE-SUPPLY ADC INTERFACE

The ADC interface on the front page shows a DC-coupled,

single-supply ADC driver circuit. Many systems are now

requiring +3V supply capability of both the ADC and its

driver. The OPA830 provides excellent performance in this

demanding application. Its large input and output voltage

ranges and low distortion support converters such as the

THS1040 shown in the figure on page 1. The input

level-shifting circuitry was designed so that VIN can be

between 0V and 0.5V, while delivering an output voltage

of 1V to 2V for the THS1040.

DC LEVEL-SHIFTING

Figure 4 shows a DC-coupled noninverting amplifier that

level-shifts the input up to accommodate the desired

output voltage range. Given the desired signal gain (G),

and the amount VOUT needs to be shifted up (∆VOUT)

when VIN is at the center of its range, the following

equations give the resistor values that produce the desired

performance. Assume that R4 is between 200Ω and

1.5k

Ω.

NG = G + VOUT/VS

R1 = R4/G

R2 = R4/(NG − G)

R3 = R4/(NG −1)

where:

NG = 1 + R4/R3

VOUT = (G)VIN + (NG − G)VS

Make sure that VIN and VOUT stay within the specified

input and output voltage ranges.

OPA830

OUT

Figure 4. DC Level-Shifting

The circuit on the front page is a good example of this type

of application. It was designed to take VIN between 0V and

0.5V and produce VOUT between 1V and 2V when using

+3V

supply.

This

means

2.00,

and

∆VOUT = 1.50V − G × 0.25V = 1.00V. Plugging these

values into the above equations (with R4 = 750Ω) gives:

NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The

resistors were changed to the nearest standard values for

the front page circuit.

AC-COUPLED OUTPUT VIDEO LINE DRIVER

Low-power and low-cost video line drivers often buffer

digital-to-analog converter (DAC) outputs with a gain of 2

into a doubly-terminated line. Those interfaces typically

require a DC blocking capacitor. For a simple solution, that

interface often has used a very large value blocking

capacitor (220

µF) to limit tilt, or SAG, across the frames.

One approach to creating a very low high-pass pole

location using much lower capacitor values is shown in

Figure 5. This circuit gives a voltage gain of 2 at the output

pin with a high-pass pole at 8Hz. Given the 150

Ω load, a

simple blocking capacitor approach would require a 133

µF

value. The two much lower valued capacitors give this

same low-pass pole using this simple SAG correction

circuit of Figure 5.

OPA830IDBVT Datasheet(PDF) 20 Page - Texas Instruments

OPA830IDBVT Datasheet(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL