OPA830IDBVT datasheet(25/35 Pages) TI

25 / 35 page

OPA830

SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

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is to isolate the capacitive load from the feedback loop by

inserting a series isolation resistor between the amplifier

output and the capacitive load.

The Typical Characteristic curves show the recommended

RS versus capacitive load and the resulting frequency

response at the load. Parasitic capacitive loads greater

than 2pF can begin to degrade the performance of the

OPA830. Long PC board traces, unmatched cables, and

connections to multiple devices can easily exceed this

value. Always consider this effect carefully, and add the

recommended series resistor as close as possible to the

output pin (see the Board Layout Guidelines section).

The criterion for setting this RS resistor is a maximum

bandwidth, flat frequency response at the load. For a gain

of +2, the frequency response at the output pin is already

slightly peaked without the capacitive load, requiring

relatively high values of RS to flatten the response at the

load. Increasing the noise gain will also reduce the peaking

(see Figure 7).

DISTORTION PERFORMANCE

The OPA830 provides good distortion performance into a

150

Ω load. Relative to alternative solutions, it provides

exceptional

performance

into

lighter

loads

and/or

operating on a single +3V supply. Generally, until the

fundamental signal reaches very high frequency or power

levels, the 2nd-harmonic will dominate the distortion with

a negligible 3rd-harmonic component. Focusing then on

the 2nd-harmonic, increasing the load impedance

improves distortion directly. Remember that the total load

includes the feedback network; in the noninverting

configuration (see Figure 3) this is sum of RF + RG, while

in the inverting configuration, only RF needs to be included

in parallel with the actual load. Running differential

suppresses the 2nd-harmonic, as shown in the differential

typical characteristic curves.

NOISE PERFORMANCE

High slew rate, unity-gain stable, voltage-feedback op

amps usually achieve their slew rate at the expense of a

higher input noise voltage. The 9.2nV/

√Hz input voltage

noise for the OPA830 however, is much lower than

comparable amplifiers. The input-referred voltage noise

and the two input-referred current noise terms (2.8pA/

√Hz)

combine to give low output noise under a wide variety of

operating conditions. Figure 10 shows the op amp noise

analysis model with all the noise terms included. In this

model, all noise terms are taken to be noise voltage or

current density terms in either nV/

√Hz or pA/√Hz.

4kT

OPA830

4kT = 1.6E

− 20J

at 290

4kTR

√

4kTR

√

Figure 10. Noise Analysis Model

The total output spot noise voltage can be computed as the

square root of the sum of all squared output noise voltage

contributors. Equation 4 shows the general form for the

output noise voltage using the terms shown in Figure 10:

O +

ENI

2 ) I

BNRS

) 4kTR

NG2

) I

BIRF

) 4kTR

FNG

Dividing

this

expression

the

noise

gain

(NG = (1 + RF/RG)) will give the equivalent input-referred

spot noise voltage at the noninverting input, as shown in

Equation 5:

N +

2 ) I

BNRS

) 4kTR

S )

BIRF

)

4kTR

Evaluating these two equations for the circuit and

component values shown in Figure 1 will give a total output

spot noise voltage of 19.3nV/

√Hz and a total equivalent

input spot noise voltage of 9.65nV/

√Hz. This is including

the noise added by the resistors. This total input-referred

spot noise voltage is not much higher than the 9.2nV/

√Hz

specification for the op amp voltage noise alone.

DC ACCURACY AND OFFSET CONTROL

The balanced input stage of a wideband voltage-feedback

op amp allows good output DC accuracy in a wide variety

of applications. The power-supply current trim for the

OPA830 gives even tighter control than comparable

products. Although the high-speed input stage does

require relatively high input bias current (typically 5

µA out

of each input terminal), the close matching between them

may be used to reduce the output DC error caused by this

current. This is done by matching the DC source

resistances appearing at the two inputs. Evaluating the

configuration of Figure 3 (which has matched DC input

(4)

(5)

OPA830IDBVT Datasheet(PDF) 25 Page - Texas Instruments

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