OPA830IDBVT datasheet(24/35 Pages) TI

24 / 35 page

OPA830

SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

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OPA830

Ω Source

750

Ω

374

Ω

1.5k

Ω

57.6

Ω

+5V

1.5k

Ω

150

Ω

0.1

µF

6.8

µF

0.1

µF

0.1

µF

Figure 9. AC-Coupled, G = −2 Example Circuit

the

inverting

configuration,

three

key

design

considerations must be noted. The first consideration is

that the gain resistor (RG) becomes part of the signal

channel input impedance. If input impedance matching is

desired (which is beneficial whenever the signal is coupled

through a cable, twisted pair, long PC board trace, or other

transmission line conductor), RG may be set equal to the

required termination value and RF adjusted to give the

desired gain. This is the simplest approach and results in

optimum bandwidth and noise performance.

However, at low inverting gains, the resulting feedback

resistor value can present a significant load to the amplifier

output. For an inverting gain of 2, setting RG to 50Ω for

input matching eliminates the need for RM but requires a

100

Ω feedback resistor. This configuration has the

interesting advantage of the noise gain becoming equal to

2 for a 50

Ω source impedance—the same as the

noninverting circuits considered above. The amplifier

output will now see the 100

Ω feedback resistor in parallel

with the external load. In general, the feedback resistor

should be limited to the 200

Ω to 1.5kΩ range. In this case,

it is preferable to increase both the RF and RG values, as

shown in Figure 9, and then achieve the input matching

impedance with a third resistor (RM) to ground. The total

input impedance becomes the parallel combination of RG

and RM.

The second major consideration, touched on in the

previous paragraph, is that the signal source impedance

becomes part of the noise gain equation and hence

influences the bandwidth. For the example in Figure 9, the

RM value combines in parallel with the external 50Ω

source impedance (at high frequencies), yielding an

effective driving impedance of 50

Ω || 57.6Ω = 26.8Ω. This

impedance is added in series with RG for calculating the

noise gain. The resulting noise gain is 2.87 for Figure 9, as

opposed to only 2 if RM could be eliminated as discussed

above. The bandwidth will therefore be lower for the gain

of −2 circuit of Figure 9 (NG = +2.87) than for the gain of

+2 circuit of Figure 1.

The third important consideration in inverting amplifier

design is setting the bias current cancellation resistors on

the

noninverting

input

parallel

combination

RT = 750Ω). If this resistor is set equal to the total DC

resistance looking out of the inverting node, the output DC

error, due to the input bias currents, will be reduced to

(Input Offset Current) times RF. With the DC blocking

capacitor in series with RG, the DC source impedance

looking out of the inverting mode is simply RF = 750Ω for

Figure 9. To reduce the additional high-frequency noise

introduced by this resistor and power-supply feed-through,

RT is bypassed with a capacitor.

OUTPUT CURRENT AND VOLTAGES

The

OPA830

provides

outstanding

output

voltage

capability. For the +5V supply, under no-load conditions at

+25

°C, the output voltage typically swings closer than

90mV to either supply rail.

The minimum specified output voltage and current

specifications over temperature are set by worst-case

simulations at the cold temperature extreme. Only at cold

startup will the output current and voltage decrease to the

numbers shown in the ensured tables. As the output

transistors deliver power, their junction temperatures will

increase, decreasing their VBEs (increasing the available

output voltage swing) and increasing their current gains

(increasing the available output current). In steady-state

operation, the available output voltage and current will

always be greater than that shown in the over-temperature

specifications,

since

the

output

stage

junction

temperatures will be higher than the minimum specified

operating ambient.

To maintain maximum output stage linearity, no output

short-circuit protection is provided. This will not normally

be a problem, since most applications include a series

matching resistor at the output that will limit the internal

power dissipation if the output side of this resistor is

shorted to ground. However, shorting the output pin

directly to the adjacent positive power-supply pin (8-pin

packages) will, in most cases, destroy the amplifier. If

additional short-circuit protection is required, consider a

small series resistor in the power-supply leads. This will

reduce the available output voltage swing under heavy

output loads.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC—including

additional external capacitance which may be recom-

mended to improve ADC linearity. A high-speed, high

open-loop gain amplifier like the OPA830 can be very

susceptible to decreased stability and closed-loop

response peaking when a capacitive load is placed directly

on the output pin. When the primary considerations are

frequency response flatness, pulse response fidelity,

and/or distortion, the simplest and most effective solution

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