OPA830IDBVT datasheet(26/35 Pages) TI

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OPA830

SBOS263F − AUGUST 2004 − REVISED AUGUST 2008

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resistances), using worst-case +25

°C input offset voltage

and current specifications, gives a worst-case output

offset voltage equal to:

(NG = noninverting signal gain at DC)

±(NG × VOS(MAX)) + (RF × IOS(MAX))

±(2 × 7mV) × (375Ω × 1µA)

±14.38mV

A fine-scale output offset null, or DC operating point

adjustment, is often required. Numerous techniques are

available for introducing DC offset control into an op amp

circuit. Most of these techniques are based on adding a DC

current through the feedback resistor. In selecting an offset

trim method, one key consideration is the impact on the

desired signal path frequency response. If the signal path

is intended to be noninverting, the offset control is best

applied as an inverting summing signal to avoid interaction

with the signal source. If the signal path is intended to be

inverting, applying the offset control to the noninverting

input may be considered. Bring the DC offsetting current

into the inverting input node through resistor values that

are much larger than the signal path resistors. This will

insure that the adjustment circuit has minimal effect on the

loop gain and hence the frequency response.

THERMAL ANALYSIS

Maximum desired junction temperature will set the

maximum

allowed

internal

power

dissipation,

described below. In no case should the maximum junction

temperature be allowed to exceed 150

°C.

Operating junction temperature (TJ) is given by

TA +PD × qJA. The total internal power dissipation (PD)

is the sum of quiescent power (PDQ) and additional

power dissipated in the output stage (PDL) to deliver load

power. Quiescent power is simply the specified no-load

supply current times the total supply voltage across the

part. PDL will depend on the required output signal and

load;

though,

for

resistive

loads

connected

mid-supply (VS/2), PDL is at a maximum when the output

is fixed at a voltage equal to VS/4 or 3VS/4. Under this

condition, PDL =VS2/(16 × RL), where RL includes

feedback network loading.

Note that it is the power in the output stage, and not into the

load, that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using

an OPA830 (SOT23-5 package) in the circuit of Figure 1

operating at the maximum specified ambient temperature

of +85

°C and driving a 150Ω load at mid-supply.

PD = 10V × 3.9mA + 52/(16 × (150Ω || 750Ω)) = 51.5mW

Maximum TJ = +85°C + (0.051W × 150°C/W) = 93°C.

Although this is still well below the specified maximum

junction temperature, system reliability considerations

may require lower ensured junction temperatures. The

highest possible internal dissipation will occur if the load

requires current to be forced into the output at high output

voltages or sourced from the output at low output voltages.

This puts a high current through a large internal voltage

drop in the output transistors.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency

amplifier like the OPA830 requires careful attention to

board layout parasitics and external component types.

Recommendations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the

output and inverting input pins can cause instability: on the

noninverting input, it can react with the source impedance

to cause unintentional bandlimiting. To reduce unwanted

capacitance, a window around the signal I/O pins should

be opened in all of the ground and power planes around

those pins. Otherwise, ground and power planes should

be unbroken elsewhere on the board.

b) Minimize the distance ( < 0.25”) from the power-supply

pins to high-frequency 0.1

µF decoupling capacitors. At the

device pins, the ground and power-plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. Each power-

supply connection should always be decoupled with one

of these capacitors. An optional supply decoupling

capacitor (0.1

µF) across the two power supplies (for

bipolar operation) will improve 2nd-harmonic distortion

performance.

Larger

(2.2

µF to 6.8µF) decoupling

capacitors, effective at lower frequency, should also be

used on the main supply pins. These may be placed

somewhat farther from the device and may be shared

among several devices in the same area of the PC board.

c) Careful selection and placement of external

components will preserve the high-frequency perfor-

mance. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter

overall

layout.

Metal

film

carbon

composition

axially-leaded resistors can also provide good high-

frequency performance. Again, keep their leads and PC

board traces as short as possible. Never use wire-wound

type resistors in a high-frequency application. Since the

output pin and inverting input pin are the most sensitive to

parasitic capacitance, always position the feedback and

series output resistor, if any, as close as possible to the

output

pin.

Other

network

components,

such

noninverting input termination resistors, should also be

placed

close to the package. Where double-side

component mounting is allowed, place the feedback

resistor directly under the package on the other side of the

board between the output and inverting input pins. Even

with a low parasitic capacitance shunting the external

resistors, excessively high resistor values can create

OPA830IDBVT Datasheet(PDF) 26 Page - Texas Instruments

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