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AD9125

Rev. 0 | Page 39 of

QUADRATURE PHASE CORRECTION

The purpose of the quadrature phase correction block is to

enable compensation of the phase imbalance of the analog

quadrature modulator following the DAC. If the quadrature

modulator has a phase imbalance, the unwanted sideband appears

with significant energy. Tuning the quadrature phase adjust value

can optimize image rejection in single sideband radios.

Ordinarily, the I and Q channels have an angle of precisely 90°

between them. The quadrature phase adjustment is used to

change the angle between the I and Q channels. When the

I phase adjust[9:0] is set to 1000000000, the I DAC output

moves approximately 1.75° away from the Q DAC output,

creating an angle of 91.75° between the channels. When the I

phase adjust[9:0] is set to 0111111111, the I DAC output moves

approximately 1.75° toward the Q DAC output, creating an

angle of 88.25° between the channels.

The Q phase adjust bits (Bits[9:0]) work in a similar fashion.

When the Q phase adjust[9:0]) is set to 1000000000, the Q DAC

output moves approximately 1.75° away from the I DAC output,

creating an angle of 91.75° between the channels. When the

Q phase adjust[9:0] is set to 0111111111, the Q DAC output

moves approximately 1.75° toward the I DAC output, creating

an angle of 88.25° between the channels.

Based on these two endpoints, the combined resolution of the

phase compensation register is approximately 3.5°/1024, or

0.00342°, per code.

DC OFFSET CORRECTION

The dc value of the I datapath and the Q datapath can be inde-

pendently controlled by adjusting the I DAC offset[15:0] and

Q DAC offset[15:0] values in Register 0x3C through Register 0x3F.

These values are added directly to the datapath values. Care should

be taken not to overrange the transmitted values.

Figure 61 shows how the DAC offset current varies as a function of

the I DAC offset[15:0] and Q DAC offset[15:0] values. With the

digital inputs fixed at midscale (0x0000, twos complement data

format), Figure 61 shows the nominal IOUTxP and IOUTxN currents

as the DAC offset value is swept from 0 to 65,535. Because IOUTxP

and IOUTxN are complementary current outputs, the sum of IOUTxP

and IOUTxN is always 20 mA.

0x0000

0x4000

0x8000

0xC000

0xFFFF

DAC OFFSET VALUE

Figure 61. DAC Output Currents vs. DAC Offset Value

INVERSE SINC FILTER

The inverse sinc (sinc−1) filter is a nine-tap FIR filter. The

composite response of the sinc−1 and the sin(x)/x response of

the DAC is shown in Figure 62. The composite response has less

than ±0.05 dB pass-band ripple up to a frequency of 0.4 × fDACCLK.

To provide the necessary peaking at the upper end of the pass

band, the inverse sinc filters have an intrinsic insertion loss of

about 3.2 dB. Figure 62 shows the composite frequency response.

–3.0

–3.2

–3.4

–3.6

–3.8

–4.0

0.3

0.4

0.2

0.1

fOUT/fDAC

Figure 62. Sample Composite Responses of the Sinc−1 Filter with Sin(x)/x Roll-Off

The sinc−1 filter is enabled by default. It can be bypassed by setting

the bypass sinc−1 bit (Register 0x1B, Bit 6).

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