AD9125 datasheet(9/56 Pages) AD

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AD9125

Rev. 0 | Page 9 of

Pin No.

Mnemonic

Description

No Connect.

DVDD18

1.8 V Digital Supply.

DVSS

Digital Common.

D15

Data Bit 15.

D14

Data Bit 14.

D13

Data Bit 13.

D12

Data Bit 12.

D11

Data Bit 11.

D10

Data Bit 10.

Data Bit 9.

Data Bit 8.

Data Bit 7.

Data Bit 6.

Data Bit 5.

Data Bit 4.

DVDD18

1.8 V Digital Supply.

DVSS

Digital Supply Common.

Data Bit 3.

Data Bit 2.

Data Bit 1.

Data Bit 0.

DVDD18

1.8 V Digital Supply.

SDO

Serial Port Data Output (CMOS levels with respect to IOVDD).

SDIO

Serial Port Data Input/Output (CMOS levels with respect to IOVDD).

SCLK

Serial Port Clock Input (CMOS levels with respect to IOVDD).

Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD).

RESET

Reset. Active Low (CMOS levels with respect to IOVDD).

No Connect.

AVSS

Analog Supply Common.

AVDD33

3.3 V Analog Supply.

IOUT2P

Q DAC Positive Current Output.

IOUT2N

Q DAC Negative Current Output.

AVDD33

3.3 V Analog Supply.

AVSS

Analog Supply Common.

REFIO

Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common.

FSADJ

Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common.

AVSS

Analog Common.

AVDD33

3.3 V Analog Supply.

IOUT1N

I DAC Negative Current Output.

IOUT1P

I DAC Positive Current Output.

AVDD33

3.3 V Analog Supply.

REFCLKN

PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input.

REFCLKP

PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input.

CVDD18

1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.

CVDD18

1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry.

EPAD

Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection

to the PCB.

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