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AD9125 Datasheet(PDF) 19 Page - Analog Devices |
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AD9125 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 56 page  AD9125 Rev. 0 | Page 19 of 56 DEVICE CONFIGURATION REGISTER MAP Table 10. Device Configuration Register Map Register Name Addr (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Comm 0x00 SDIO LSB_FIRST Reset 0x00 Power Control 0x01 Power- down DAC I Power- down DAC Q Power- down data receiver Power- down aux ADC PLL lock status 0x10 Data Format 0x03 Binary data format Q data first MSB swap Data bus width[1:0] 0x00 Interrupt Enable 1 0x04 Enable PLL lock lost Enable PLL lock Enable sync signal lost Enable sync signal lock Enable sync phase lock Enable soft FIFO sync Enable FIFO Warning1 Enable FIFO Warning 2 0x00 Interrupt Enable 2 0x05 0 0 0 Enable AED compare pass Enable AED compare fail Enable SED compare fail 0 0 0x00 Event Flag 1 0x06 PLL lock lost PLL locked Sync signal lost Sync signal locked Sync phase locked Soft FIFO sync FIFO Warning1 FIFO Warning 2 N/A Event Flag 2 0x07 AED compare pass AED compare fail SED compare fail N/A Clock Receiver Control 0x08 DACCLK duty correction REFCLK duty correction DACCLK cross- correction REFCLK cross- correction 1 1 1 1 0x3F PLL Control 1 0x0A PLL enable PLL manual enable Manual VCO band[5:0] 0x40 PLL Control 2 0x0C PLL loop bandwidth[2:0] PLL charge pump current[4:0] 0xD1 PLL Control 3 0x0D N2[1:0] PLL cross control enable N0[1:0] N1[1:0] 0xD9 PLL Status 1 0x0E PLL lock VCO control voltage[3:0] 0x00 PLL Status 2 0x0F VCO band readback[5:0] 0x00 Sync Control 1 0x10 Sync enable Data/FIFO rate toggle Rising edge sync Sync Averaging[2:0] 0x48 Sync Control 2 0x11 Sync phase request[5:0] 0x00 Sync Status 1 0x12 Sync lost Sync locked N/A Sync Status 2 0x13 Sync phase readback[7:0] (6.2 format) N/A FIFO Control 0x17 FIFO phase offset[2:0] 0x04 FIFO Status 1 0x18 FIFO Warning 1 FIFO Warning 2 FIFO soft align ack FIFO soft align request FIFO reset aligned N/A FIFO Status 2 0x19 FIFO level[7:0] N/A Datapath Control 0x1B Bypass premod Bypass sinc−1 Bypass NCO NCO gain Bypass phase compen- sation and dc offset Select sideband Send I data to Q data 0xE4 HB1 Control 0x1C HB1[1:0] Bypass HB1 0x00 HB2 Control 0x1D HB2[5:0] Bypass HB2 0x00 HB3 Control 0x1E HB3[5:0] Bypass HB3 0x00 Chip ID 0x1F Chip ID[7:0] 0x08 |
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