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PT2579 V1.6

- 5 -

May, 2008

RDS Demodulator IC

PT2579

TIMING

The fixed and variable dividers are applied to the 4.332/8.664MHz crystal oscillator to generate the

1.1875KHz RDS Clock – RDCL. The RDCL is synchronized with the incoming data. No matter what

clock edge is considered, the data will be valid for a period of 399 us after clock transition. The data

change timing is 4µs before a clock change. Which clock transition (i.e. positive or negative going

clock), the data change occurs in, depends on the lock conditions and is arbitrary (bit slip).

When the reception is poor, it is possible that faults in phase occur, then the clock signal stays

uninterrupted and data is constant for 1.5 clock periods. Normally, faults in phase do not occur in a

cyclic manner. If however, the faults in the phase occur in this way, the minimum spacing between two

possible faults in phase depends on the data being transmitted. The minimum spacing cannot be less

than 16 clock period. The quality bit changes only at the time of a data change.

The diagram below shows the RDS timing waveform which includes a phase jump.

4s

µ

421 s

µ

4s

µ 842 s

µ

RDDA

QUAL

RDCL