HMP8154 datasheet(13/34 Pages) INTERSIL

13 / 34 page

The delay from the active edge of HSYNC to the 50% point

of the composite sync is 4-39 CLK2 cycles depending on the

HMP8154/HMP8156A operating mode. The delay is shortest

when the encoder is the timing master; it is longest when in

slave mode.

Flicker Filter Blanking

When the flicker filter is enabled, BLANK occurs twice per line.

However, HSYNC does not change and still matches the

horizontal syncs of the composite output. The default timing of

BLANK with respect to HSYNC is shown in Figure 16.

Only the ﬁrst unblanked period during each line time

determines when the active video will be output. Because of

the half line offset between the H and V syncs, pixel data

input begins (blanking ends) in the middle of the line time for

odd ﬁelds. However, it is still the unblanked period

immediately after HSYNC which generates the active region

of the output video. During even ﬁelds, the unblanking pulses

for the even numbered lines determine the output timing;

during odd ﬁelds, it’s the odd numbered lines.

When it is an output and the ﬂicker ﬁlter is enabled, BLANK

generation is similar to that found in normal mode. The main

difference is that the encoder counts every CLK2 instead of

every other CLK2. The start and end times for each line’s

second unblanked interval are shifted slightly. The

unblanked intervals are the same number of pixels but the

blanked intervals are not. The count values for BLANK

transitions are shown in Figure 17.

CLK2 Input Timing

The CLK2 input clocks all of the HMP8154/HMP8156A,

including its video timing counters. For proper operation, all

of the HMP8154/HMP8156A inputs must be synchronous

with CLK2. The frequency of CLK2 depends on the device’s

operating mode and the total number of pixels per line. The

standard clock frequencies are shown in Table 7.

Note that the color subcarrier is derived from the CLK2 input.

Any jitter on CLK2 will be transferred to the color subcarrier,

resulting in color changes. Just 400ps of jitter on CLK2 causes

up to a 1 degree color subcarrier phase shift. Thus, CLK2

should be derived from a stable clock source, such as a crystal.

The use of a PLL to generate CLK2 is not recommended.

Video Processing

Upsampling

Video processing begins with the 4:4:4 sampled YCbCr data

from the input processor. After overlay mixing and optional

2X upscaling or ﬂicker ﬁltering, the HMP8154/HMP8156A

upsamples the 4:4:4 data to generate 8:8:8 data. The

encoder uses linear interpolation for the upsampling.

Horizontal Filtering

Unless disabled, the HMP8154/HMP8156A lowpass ﬁlters

the Y data to 6.0MHz. Lowpass ﬁltering Y removes any

aliasing artifacts due to the upsampling process, and

simpliﬁes the analog output ﬁlters. The Y 6.0MHz lowpass

ﬁlter response is shown in Figure 18. At this point, the

HMP8154/HMP8156A also scales the Y data to generate

the proper output levels for the various video standards

The HMP8154/HMP8156A lowpass filters the Cb and Cr

data to 1.3MHz prior to modulation. The lowpass filtering

removes any aliasing artifacts due to the upsampling

process (simplifying the analog output filters) and also

properly bandwidth-limits Cb and Cr prior to modulation.

The chrominance filtering is not optional like luminance

filtering. The Cb and Cr 1.3MHz lowpass filter response is

shown in Figure 19.

FIGURE 16A. BEGINNING AN EVEN FIELD

HSYNC

BLANK

FIELD

†

PIXEL

LINE #

DATA

FIGURE 16. HSYNC AND BLANK TIMING WITH THE FLICKER

FILTER ENABLED. VSYNC ALIGNS WITH EITHER

EDGE OF FIELD.

† UNBLANKED PERIOD WHICH

DETERMINES ACTIVE VIDEO IN OUTPUT.

FIGURE 16B. BEGINNING AN ODD FIELD

HSYNC

BLANK

FIELD

†

PIXEL

LINE #

DATA

FIGURE 17. FLICKER FILTER BLANK OUTPUT TIMING

COUNTS. TOTAL DEPENDS ON FORMAT.

ACTIVE = START_H_BLANK -- END_H_BLANK

HSYNC

BLANK

END_H_BLANK / 2

END_H_BLANK

END_H_BLANK / 2 +

START_H_BLANK

TOTAL

TOTAL -- ACTIVE

HMP8154, HMP8156A

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