15

FN6666.4

December 22, 2008

needs to match the inductor time constant L/DCR. The value

For example, if L is 1.5µH, DCR is 4.5m

9k

prevent false OCP during this time, a 10µA current source

flows out of the OUT1 pin, generating a voltage drop on the

OUT1 pin current source will be removed.

When an OCP fault is declared, the PGOOD pin will pull-down

to 32

Ω and latch-off the converter. The fault will remain

latched until the EN pin has been pulled below the falling EN

POR threshold.

When using a discrete current sense resistor, inductor

time-constant matching is not required. Equation 7 remains

unchanged, but Equation 8 is modified in Equation 11:

Furthermore, Equation 9 is changed in Equation 12:

Overvoltage Protection

The OVP fault detection circuit triggers after the FB pin

voltage is above the rising overvoltage threshold for more

than 2µs. The FB pin voltage is 0.6V in normal operation.

The rising overvoltage threshold is typically 116% of that

value, or 1.16*0.6V = 0.696V.

For both the ISL62391 and ISL62392, when an OVP fault is

declared, the PGOOD pin will pull-down with 32

Ω and latch-off

the converter. The OVP fault will remain latched until the EN

pin has been pulled below the falling EN threshold voltage, or

the latch condition, the ISL62391 will tri-state the PHASE

node by turning both UGATE and LGATE off until the latch is

cleared.

Although latched, the ISL62392 LGATE gate-driver output will

retain the ability to toggle the low-side MOSFET on and off in

response to the output voltage transversing the OVP rising

and falling thresholds. The LGATE gate-driver will turn on the

low-side MOSFET to discharge the output voltage, thus

protecting the load from potentially damaging voltage levels.

The LGATE gate-driver will turn off the low-side MOSFET

once the FB pin voltage is lower than the falling overvoltage

threshold for more than 2µs. The falling overvoltage threshold

is typically 106% of the reference voltage, or 1.06*0.6V =

0.636V. This soft-crowbar process repeats as long as the

output voltage fault is present, allowing the ISL62392 to

protect against persistent overvoltage conditions.

Undervoltage Protection

The UVP fault detection circuit triggers after the FB pin

voltage is below the undervoltage threshold for more than

2µs. The undervoltage threshold is typically 86% of the

reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is

declared, the PGOOD pin will pull-down with 32

Ω and latch-off

the converter. The fault will remain latched until the EN pin

has decayed below the falling POR threshold.

Programming the Output Voltage

When the converter is in regulation, there will be 0.6V

between the FB and GND pins. Connect a two-resistor

voltage divider across the OUT and GND pins with the

output node connected to the FB pin, as shown in Figure 27.

Scale the voltage-divider network such that the FB pin is

0.6V with respect to the GND pin when the converter is

regulating at the desired output voltage. The output voltage

can be programmed from 0.6V to 5.5V.

Programming the output voltage is written as Equation 13:

Where:

- The voltage to which the converter regulates the FB pin

from the FB pin to the converter output. In addition to

setting the output voltage, this resistor is part of the loop

compensation network

connects from the FB pin to the GND pin

Compensation Design

Figure 27 shows the recommended Type-II compensation

circuit. The FB pin is the inverting input of the error amplifier.

The COMP signal, the output of the error amplifier, is inside the

integrated inside the IC that connects across the FB pin and the

compensator. The frequency domain transfer function is given

by Equation 15:

(EQ. 10)

C

SEN

L

R

•

-----------------------------------------

=

V

–

OUT1

I

•

10

μAR

OCSET

•

–

=

(EQ. 11)

R

OCSET

I

•

10

μA

-------------------------------------

=

(EQ. 12)

V

OUT

V

REF

1

R

TOP

R

BOTTOM

-----------------------------

+

⎝⎠

⎜⎟

⎛⎞

•

=

(EQ. 13)

R

BOTTOM

V

•

TOP

V

OUT

V

REF

–

-------------------------------------

=

(EQ. 14)

(EQ. 15)

G

()

1s

R

TOP

R

FB

+

() C

•

FB

•

+

sR

1s R

•

FB

•

+

()

•

•

•

-------------------------------------------------------------------------------------------

=

ISL62391, ISL62392