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DS2156 Datasheet(PDF) 45 Page - Maxim Integrated Products

Part # DS2156
Description  T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
PDF  265 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS2156 Datasheet(HTML) 45 Page - Maxim Integrated Products

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4.2
UTOPIA Bus Registers
When the UTOPIA bus is enabled, register space 50h–6A is mapped to the UTOPIA function.
Table 4-B. UTOPIA Register Map
ADDRESS
xxh
R/W
REGISTER
SYMBOL
PAGE
50
R/W
Transmit Configuration Register
U_TCFR
182
51
R/W
Transmit PMON Counter-Latch Enable Register
U_TPCLE
183
52
W
Transmit Assigned Cell Counter MSB
U_TACC1
183
53
R
Transmit Assigned Cell Counter LSB
U_TACC2
183
54
R
Transmit Idle/Unassigned Payload Byte
U_TIUPB
184
55
R/W
Transmit HEC Error-Insertion Pattern
U_THEPR
184
56
R/W
Transmit Control Register 1
U_TCR1
185
57
R/W
Transmit Control Register 2
U_TCR2
186
58, 59,
5A–5F
—
Reserved
—
—
60
R/W
Receive Configuration Register
U_RCFR
186
61
R/W
Receive LCD Integration Period Register
U_RLCDIP
187
62
R/W
Receive PMON Counter-Latch Enable Register
U_RPCE
187
63
W
Receive Correctable HEC Latch Register
U_RCHEC
188
64
R
Receive Uncorrectable HEC MSB
U_RUHEC1
188
65
R
Receive Uncorrectable HEC LSB
U_RUHEC2
188
66
R
Receive Assigned Cell Counter MSB
U_RACC1
189
67
R
Receive Assigned Cell Counter LSB
U_RACC2
189
68
R
Receive Status Register
U_RSR
190
69
R
Receive Control Register 1
U_RCR1
191
6A
R/W
Receive Control Register 2
U_RCR2
192
6B–6F
—
Reserved
—
—



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