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TDA8023 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # TDA8023
Description  Low power IC card interface
PDF  32 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDA8023 Datasheet(HTML) 8 Page - NXP Semiconductors

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TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
8 of 32
NXP Semiconductors
TDA8023
Low power IC card interface
8.2.4 Shutdown mode
When pin SDWN = HIGH, the TDA8023 is in Shutdown mode; the consumption in this
mode is less than 10
µA. The I2C-bus is unresponsive.
If the card is extracted or inserted when the TDA8023 is in Power-down mode, pin INT
becomes LOW and stays LOW as long as pin SDWN = HIGH.
When pin SDWN is pulled LOW, the TDA8023 leaves Shutdown mode and executes a
complete power-on reset sequence.
8.3 I2C-bus
A 400 kHz I2C-bus slave interface is used for configuring the TDA8023 and reading the
status.
8.3.1 I2C-bus protocol
The I2C-bus is for 2-way 2-line communication between ICs or modules. The serial bus
consists of two bidirectional lines: one for data signals (SDA) and one for clock signals
(SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy
• During data transfer, the data line must remain stable whenever the clock line is
HIGH; changes in the data line while the clock line is HIGH will be interpreted as
control signals
8.3.2 Bus conditions
The following bus conditions have been defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line from HIGH to LOW, while the
clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line from LOW to HIGH, while the
clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock signal.
There is one clock pulse per bit of data.
8.3.3 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition (see Figure 7). See Table 15 for timing information.
Data transfer is unlimited in the Read mode. The information is transmitted in bytes and
each receiver acknowledges with a 9th bit.



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