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Z550 Datasheet(PDF) 23 Page - Intel Corporation |
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Z550 Datasheet(HTML) 23 Page - Intel Corporation |
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23 / 73 page ![]() Low Power Features Datasheet 23 2.3 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep® Technology. The following are the key features of Enhanced Intel SpeedStep® Technology: • Multiple voltage and frequency operating points providing optimal performance at the lowest power. • Voltage and frequency selection is software controlled by writing to processor MSRs: If the target frequency is higher than the current frequency, VCC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes. • The processor controls voltage ramp rates internally to ensure glitch free transitions. • Low transition latency and a large number of transitions are possible per second: Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency transition. — The bus protocol (BNR# mechanism) is used to block snooping. • Improved Intel Thermal Monitor mode: When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR. The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency and voltage point occurs. An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management. • Enhanced thermal management features: Digital Thermal Sensor and Out of Specification detection Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. |
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