Z550 datasheet(59/73 Pages) INTEL

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Package Mechanical Specifications and Pin Information

Datasheet

Signal Name

Type

Description

FERR#/PBE#

FERR# (Floating-point Error) PBE# (Pending Break Event) is a

multiplexed signal and its meaning is qualified with STPCLK#.

When STPCLK# is not asserted, FERR#/PBE# indicates a floating

point when the processor detects an unmasked floating-point

error. FERR# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using

MSDOS*- type floating-point error reporting. When STPCLK# is

asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The

assertion of FERR#/PBE# indicates that the processor should be

returned to the Normal state. When FERR#/PBE# is asserted,

indicating a break event, it will remain asserted until STPCLK# is

de-asserted. Assertion of PREQ# when STPCLK# is active will

also cause an FERR# break event.

For additional information on the pending break event

functionality, including identification of support of the feature and

enable/disable information, refer to Volume 3 of the Intel® 64

and IA-32 Architectures Software Developer's Manuals and the

Intel® Processor Identification and CPUID Instruction Application

Note.

CMREF

PWR

CMREF determines the signal reference level for CMOS input

pins. CMREF should be set at 1/2 VCCP. CMREF is used by the

CMOS receivers to determine if a signal is a logical 0 or logical 1.

If not using CMOS, then all CMREF and GTLREF should be

provided with 2/3 VCCP.

GTLREF

PWR

GTLREF determines the signal reference level for AGTL+ input

pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the

AGTL+ receivers to determine if a signal is a logical 0 or logical

HIT#

HITM#

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction

snoop operation results. Either FSB agent may assert both HIT#

and HITM# together to indicate that it requires a snoop stall,

which can be continued by reasserting HIT# and HITM#

together.

IERR#

IERR# (Internal Error) is asserted by a processor as the result of

an internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the FSB. This transaction may

optionally be converted to an external error signal (for example,

NMI) by system core logic. The processor will keep IERR#

asserted until the assertion of RESET# or INIT#.

IGNNE#

IGNNE# (Ignore Numeric Error) is asserted to force the

processor to ignore a numeric error and continue to execute non-

control floating-point instructions. If IGNNE# is de-asserted, the

processor generates an exception on a non-control floating-point

instruction if a previous floating-point instruction caused an

error. IGNNE# has no effect when the NE bit in control register 0

(CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure

recognition of this signal following an Input/Output write

instruction, it must be valid along with the TRDY# assertion of

the corresponding Input/Output Write bus transaction.

Z550 Datasheet(PDF) 59 Page - Intel Corporation

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